Search

Andrew M. Dolinar

Examiner (ID: 119)

Most Active Art Unit
3402
Art Unit(s)
3727, 3402, 3106, 3403, 3747, 2899
Total Applications
2333
Issued Applications
2180
Pending Applications
33
Abandoned Applications
120

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11791689 [patent_doc_number] => 09401331 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-26 [patent_title] => 'Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP' [patent_app_type] => utility [patent_app_number] => 14/267800 [patent_app_country] => US [patent_app_date] => 2014-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 27 [patent_no_of_words] => 10286 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14267800 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/267800
Semiconductor device and method of forming a vertical interconnect structure for 3-D FO-WLCSP Apr 30, 2014 Issued
Array ( [id] => 9617386 [patent_doc_number] => 20140207243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-24 [patent_title] => 'Implants for Altering Wear Patterns of Articular Surfaces' [patent_app_type] => utility [patent_app_number] => 14/222836 [patent_app_country] => US [patent_app_date] => 2014-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 46 [patent_no_of_words] => 24003 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14222836 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/222836
Implants for altering wear patterns of articular surfaces Mar 23, 2014 Issued
Array ( [id] => 10022408 [patent_doc_number] => 09064903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-23 [patent_title] => 'Analog floating-gate memory manufacturing process implementing n-channel and p-channel MOS transistors' [patent_app_type] => utility [patent_app_number] => 14/172608 [patent_app_country] => US [patent_app_date] => 2014-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 8896 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14172608 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/172608
Analog floating-gate memory manufacturing process implementing n-channel and p-channel MOS transistors Feb 3, 2014 Issued
Array ( [id] => 9435505 [patent_doc_number] => 20140113412 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'CHIP PACKAGE AND FABRICATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/135506 [patent_app_country] => US [patent_app_date] => 2013-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2219 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14135506 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/135506
Fabrication method for a chip package Dec 18, 2013 Issued
Array ( [id] => 9594650 [patent_doc_number] => 20140191327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/132967 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6893 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14132967 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/132967
SEMICONDUCTOR MEMORY DEVICE Dec 17, 2013 Abandoned
Array ( [id] => 9565990 [patent_doc_number] => 20140183702 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'DESIGN METHOD OF WIRING LAYOUT, SEMICONDUCTOR DEVICE, PROGRAM FOR SUPPORTING DESIGN OF WIRING LAYOUT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/133278 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 95 [patent_figures_cnt] => 95 [patent_no_of_words] => 43461 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14133278 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/133278
DESIGN METHOD OF WIRING LAYOUT, SEMICONDUCTOR DEVICE, PROGRAM FOR SUPPORTING DESIGN OF WIRING LAYOUT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Dec 17, 2013 Abandoned
Array ( [id] => 10916681 [patent_doc_number] => 20140319700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-30 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 14/132203 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 5453 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14132203 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/132203
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME Dec 17, 2013 Abandoned
Array ( [id] => 9557961 [patent_doc_number] => 20140175674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'Package on Package Device' [patent_app_type] => utility [patent_app_number] => 14/133005 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1525 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14133005 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/133005
Package on Package Device Dec 17, 2013 Abandoned
Array ( [id] => 9654162 [patent_doc_number] => 20140225167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-14 [patent_title] => 'VERTICAL ELECTROMECHANICAL SWITCH DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/133410 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4069 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14133410 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/133410
Vertical electromechanical switch device Dec 17, 2013 Issued
Array ( [id] => 9783155 [patent_doc_number] => 20140299975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-09 [patent_title] => 'Method and Board for Growing High-Quality Graphene Layer Using High Pressure Annealing' [patent_app_type] => utility [patent_app_number] => 14/132071 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4104 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14132071 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/132071
Method and board for growing high-quality graphene layer using high pressure annealing Dec 17, 2013 Issued
Array ( [id] => 9594651 [patent_doc_number] => 20140191328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/133263 [patent_app_country] => US [patent_app_date] => 2013-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9299 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14133263 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/133263
SEMICONDUCTOR MEMORY DEVICE Dec 17, 2013 Abandoned
Array ( [id] => 9565889 [patent_doc_number] => 20140183602 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'ALTERNATING TAP-CELL STRATEGY IN A STANDARD CELL LOGIC BLOCK FOR AREA REDUCTION' [patent_app_type] => utility [patent_app_number] => 14/108537 [patent_app_country] => US [patent_app_date] => 2013-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3496 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14108537 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/108537
Alternating tap-cell strategy in a standard cell logic block for area reduction Dec 16, 2013 Issued
Array ( [id] => 11510330 [patent_doc_number] => 09601496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-21 [patent_title] => 'Semiconductor device having sacrificial layer pattern with concave sidewalls and method fabricating the same' [patent_app_type] => utility [patent_app_number] => 14/109159 [patent_app_country] => US [patent_app_date] => 2013-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4919 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14109159 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/109159
Semiconductor device having sacrificial layer pattern with concave sidewalls and method fabricating the same Dec 16, 2013 Issued
Array ( [id] => 11429151 [patent_doc_number] => 09567460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Molded reflectors for light-emitting diode assemblies' [patent_app_type] => utility [patent_app_number] => 14/109510 [patent_app_country] => US [patent_app_date] => 2013-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 9378 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14109510 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/109510
Molded reflectors for light-emitting diode assemblies Dec 16, 2013 Issued
Array ( [id] => 10845157 [patent_doc_number] => 08872337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-28 [patent_title] => 'Semiconductor package and display apparatus using the same' [patent_app_type] => utility [patent_app_number] => 14/106912 [patent_app_country] => US [patent_app_date] => 2013-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 7096 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14106912 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/106912
Semiconductor package and display apparatus using the same Dec 15, 2013 Issued
Array ( [id] => 11201026 [patent_doc_number] => 09431246 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Semiconductor device with low contact resistance SIC region' [patent_app_type] => utility [patent_app_number] => 14/107552 [patent_app_country] => US [patent_app_date] => 2013-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 33 [patent_no_of_words] => 15646 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14107552 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/107552
Semiconductor device with low contact resistance SIC region Dec 15, 2013 Issued
Array ( [id] => 9305082 [patent_doc_number] => 20140043756 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-13 [patent_title] => 'ACTIVE THERMAL CONTROL FOR STACKED IC DEVICES' [patent_app_type] => utility [patent_app_number] => 14/056212 [patent_app_country] => US [patent_app_date] => 2013-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2967 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14056212 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/056212
Active thermal control for stacked IC devices Oct 16, 2013 Issued
Array ( [id] => 10652227 [patent_doc_number] => 09368492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-14 [patent_title] => 'Forming fins of different materials on the same substrate' [patent_app_type] => utility [patent_app_number] => 14/054009 [patent_app_country] => US [patent_app_date] => 2013-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3598 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14054009 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/054009
Forming fins of different materials on the same substrate Oct 14, 2013 Issued
Array ( [id] => 10212291 [patent_doc_number] => 20150097283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-09 [patent_title] => 'PLUG VIA FORMATION WITH GRID FEATURES IN THE PASSIVATION LAYER' [patent_app_type] => utility [patent_app_number] => 14/048483 [patent_app_country] => US [patent_app_date] => 2013-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6029 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14048483 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/048483
Plug via formation with grid features in the passivation layer Oct 7, 2013 Issued
Array ( [id] => 9895578 [patent_doc_number] => 20150050777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-19 [patent_title] => 'Integrated circuit package having surface-mount blocking elements' [patent_app_type] => utility [patent_app_number] => 14/048410 [patent_app_country] => US [patent_app_date] => 2013-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3482 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14048410 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/048410
Integrated circuit package having surface-mount blocking elements Oct 7, 2013 Issued
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