Search

Andrew M. Dolinar

Examiner (ID: 119)

Most Active Art Unit
3402
Art Unit(s)
3727, 3402, 3106, 3403, 3747, 2899
Total Applications
2333
Issued Applications
2180
Pending Applications
33
Abandoned Applications
120

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10557004 [patent_doc_number] => 09281207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Solution processible hardmasks for high resolution lithography' [patent_app_type] => utility [patent_app_number] => 13/407541 [patent_app_country] => US [patent_app_date] => 2012-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 51 [patent_no_of_words] => 18773 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13407541 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/407541
Solution processible hardmasks for high resolution lithography Feb 27, 2012 Issued
Array ( [id] => 9778635 [patent_doc_number] => 08853843 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Modular low stress package technology' [patent_app_type] => utility [patent_app_number] => 13/406681 [patent_app_country] => US [patent_app_date] => 2012-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 71 [patent_no_of_words] => 14894 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13406681 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/406681
Modular low stress package technology Feb 27, 2012 Issued
Array ( [id] => 10118879 [patent_doc_number] => 09153772 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-06 [patent_title] => 'Device for increasing the magnetic flux density' [patent_app_type] => utility [patent_app_number] => 13/407581 [patent_app_country] => US [patent_app_date] => 2012-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2027 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13407581 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/407581
Device for increasing the magnetic flux density Feb 27, 2012 Issued
Array ( [id] => 10171986 [patent_doc_number] => 09202698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-01 [patent_title] => 'Replacement gate electrode with multi-thickness conductive metallic nitride layers' [patent_app_type] => utility [patent_app_number] => 13/406784 [patent_app_country] => US [patent_app_date] => 2012-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9550 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13406784 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/406784
Replacement gate electrode with multi-thickness conductive metallic nitride layers Feb 27, 2012 Issued
Array ( [id] => 10010585 [patent_doc_number] => 09054112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-09 [patent_title] => 'Semiconductor device comprising a die seal having an integrated alignment mark' [patent_app_type] => utility [patent_app_number] => 13/406901 [patent_app_country] => US [patent_app_date] => 2012-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6518 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13406901 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/406901
Semiconductor device comprising a die seal having an integrated alignment mark Feb 27, 2012 Issued
Array ( [id] => 9000294 [patent_doc_number] => 20130221418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'Analog Floating-Gate Memory Manufacturing Process Implementing N-Channel and P-Channel MOS Transistors' [patent_app_type] => utility [patent_app_number] => 13/406704 [patent_app_country] => US [patent_app_date] => 2012-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8872 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13406704 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/406704
Analog floating-gate memory with N-channel and P-channel MOS transistors Feb 27, 2012 Issued
Array ( [id] => 9000419 [patent_doc_number] => 20130221543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERCONNECTS AND METHOD OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 13/407554 [patent_app_country] => US [patent_app_date] => 2012-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6786 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13407554 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/407554
Integrated circuit packaging system with interconnects Feb 27, 2012 Issued
Array ( [id] => 8379758 [patent_doc_number] => 20120223379 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-06 [patent_title] => 'NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/407187 [patent_app_country] => US [patent_app_date] => 2012-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6800 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13407187 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/407187
NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME Feb 27, 2012 Abandoned
Array ( [id] => 9000354 [patent_doc_number] => 20130221478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES BY EMPLOYING A SPIN-ON GLASS MATERIAL OR A FLOWABLE OXIDE MATERIAL' [patent_app_type] => utility [patent_app_number] => 13/405713 [patent_app_country] => US [patent_app_date] => 2012-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3364 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13405713 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/405713
METHODS OF FORMING ISOLATION STRUCTURES FOR SEMICONDUCTOR DEVICES BY EMPLOYING A SPIN-ON GLASS MATERIAL OR A FLOWABLE OXIDE MATERIAL Feb 26, 2012 Abandoned
Array ( [id] => 9876032 [patent_doc_number] => 08963304 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-24 [patent_title] => 'Semiconductor device and semiconductor device mounting structure' [patent_app_type] => utility [patent_app_number] => 13/406527 [patent_app_country] => US [patent_app_date] => 2012-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 13241 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13406527 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/406527
Semiconductor device and semiconductor device mounting structure Feb 26, 2012 Issued
Array ( [id] => 9590016 [patent_doc_number] => 08779559 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-15 [patent_title] => 'Structure and method for strain-relieved TSV' [patent_app_type] => utility [patent_app_number] => 13/405600 [patent_app_country] => US [patent_app_date] => 2012-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 4473 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13405600 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/405600
Structure and method for strain-relieved TSV Feb 26, 2012 Issued
Array ( [id] => 9000398 [patent_doc_number] => 20130221522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'MECHANISMS OF FORMING CONNECTORS FOR PACKAGE ON PACKAGE' [patent_app_type] => utility [patent_app_number] => 13/406031 [patent_app_country] => US [patent_app_date] => 2012-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5187 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13406031 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/406031
Mechanisms for forming connectors with a molding compound for package on package Feb 26, 2012 Issued
Array ( [id] => 8705482 [patent_doc_number] => 20130062771 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-14 [patent_title] => 'DESIGN METHOD OF WIRING LAYOUT, SEMICONDUCTOR DEVICE, PROGRAM FOR SUPPORTING DESIGN OF WIRING LAYOUT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/405922 [patent_app_country] => US [patent_app_date] => 2012-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 49 [patent_no_of_words] => 28976 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13405922 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/405922
DESIGN METHOD OF WIRING LAYOUT, SEMICONDUCTOR DEVICE, PROGRAM FOR SUPPORTING DESIGN OF WIRING LAYOUT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Feb 26, 2012 Abandoned
Array ( [id] => 9000375 [patent_doc_number] => 20130221499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'Semiconductor Package with Integrated Electromagnetic Shielding' [patent_app_type] => utility [patent_app_number] => 13/405721 [patent_app_country] => US [patent_app_date] => 2012-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4096 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13405721 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/405721
Semiconductor package with integrated electromagnetic shielding Feb 26, 2012 Issued
Array ( [id] => 8730349 [patent_doc_number] => 20130075918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-28 [patent_title] => 'SHIFT REGISTER MEMORY' [patent_app_type] => utility [patent_app_number] => 13/405692 [patent_app_country] => US [patent_app_date] => 2012-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6823 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13405692 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/405692
Shift register memory Feb 26, 2012 Issued
Array ( [id] => 10858156 [patent_doc_number] => 08884360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-11 [patent_title] => 'Semiconductor device with improved robustness' [patent_app_type] => utility [patent_app_number] => 13/404161 [patent_app_country] => US [patent_app_date] => 2012-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8065 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13404161 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/404161
Semiconductor device with improved robustness Feb 23, 2012 Issued
Array ( [id] => 8753502 [patent_doc_number] => 20130087806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-11 [patent_title] => 'SEMICONDUCTOR LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR LIGHT EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/404607 [patent_app_country] => US [patent_app_date] => 2012-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8229 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13404607 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/404607
Semiconductor light emitting device Feb 23, 2012 Issued
Array ( [id] => 8753501 [patent_doc_number] => 20130087805 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-11 [patent_title] => 'SEMICONDUCTOR LIGHT EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 13/404531 [patent_app_country] => US [patent_app_date] => 2012-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9226 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13404531 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/404531
Semiconductor light emitting device Feb 23, 2012 Issued
Array ( [id] => 8765051 [patent_doc_number] => 20130093088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'PACKAGE-ON-PACKAGE ASSEMBLY WITH WIRE BOND VIAS' [patent_app_type] => utility [patent_app_number] => 13/405108 [patent_app_country] => US [patent_app_date] => 2012-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 20822 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13405108 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/405108
Package-on-package assembly with wire bond vias Feb 23, 2012 Issued
Array ( [id] => 8344869 [patent_doc_number] => 20120205801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => 'Anti-Tamper Wrapper Interconnect Method and a Device' [patent_app_type] => utility [patent_app_number] => 13/370381 [patent_app_country] => US [patent_app_date] => 2012-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3405 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13370381 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/370381
Anti-tamper wrapper interconnect method and a device Feb 9, 2012 Issued
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