Search

Andrew M. Dolinar

Examiner (ID: 119)

Most Active Art Unit
3402
Art Unit(s)
3727, 3402, 3106, 3403, 3747, 2899
Total Applications
2333
Issued Applications
2180
Pending Applications
33
Abandoned Applications
120

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6569799 [patent_doc_number] => 20100273288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'IMAGER DEVICE WITH ELECTRIC CONNECTIONS TO ELECTRICAL DEVICE' [patent_app_type] => utility [patent_app_number] => 12/829560 [patent_app_country] => US [patent_app_date] => 2010-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2732 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20100273288.pdf [firstpage_image] =>[orig_patent_app_number] => 12829560 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/829560
Methods of forming imager device with electric connections to electrical device Jul 1, 2010 Issued
Array ( [id] => 8249133 [patent_doc_number] => 20120153444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/379329 [patent_app_country] => US [patent_app_date] => 2010-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 256 [patent_figures_cnt] => 256 [patent_no_of_words] => 153377 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20120153444.pdf [firstpage_image] =>[orig_patent_app_number] => 13379329 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/379329
SEMICONDUCTOR DEVICE Jun 16, 2010 Abandoned
Array ( [id] => 8808345 [patent_doc_number] => 08445998 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-05-21 [patent_title] => 'Leadframe structures for semiconductor packages' [patent_app_type] => utility [patent_app_number] => 12/712170 [patent_app_country] => US [patent_app_date] => 2010-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2727 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 360 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12712170 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/712170
Leadframe structures for semiconductor packages Feb 23, 2010 Issued
Array ( [id] => 9188894 [patent_doc_number] => 20130328209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-12 [patent_title] => 'Stack Arrangement' [patent_app_type] => utility [patent_app_number] => 13/576655 [patent_app_country] => US [patent_app_date] => 2010-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9978 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13576655 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/576655
Stack Arrangement Feb 11, 2010 Abandoned
Array ( [id] => 8270238 [patent_doc_number] => 08211740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-03 [patent_title] => 'Solid state imaging device having wirings with diffusion prevention film' [patent_app_type] => utility [patent_app_number] => 12/703105 [patent_app_country] => US [patent_app_date] => 2010-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 7569 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12703105 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/703105
Solid state imaging device having wirings with diffusion prevention film Feb 8, 2010 Issued
Array ( [id] => 6457804 [patent_doc_number] => 20100090282 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/639996 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 38 [patent_figures_cnt] => 38 [patent_no_of_words] => 19845 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20100090282.pdf [firstpage_image] =>[orig_patent_app_number] => 12639996 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/639996
SEMICONDUCTOR INTEGRATED CIRCUIT Dec 16, 2009 Abandoned
Array ( [id] => 6400747 [patent_doc_number] => 20100148312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'REINFORCED SMART CARDS & METHODS OF MAKING SAME' [patent_app_type] => utility [patent_app_number] => 12/639976 [patent_app_country] => US [patent_app_date] => 2009-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3845 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20100148312.pdf [firstpage_image] =>[orig_patent_app_number] => 12639976 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/639976
REINFORCED SMART CARDS & METHODS OF MAKING SAME Dec 15, 2009 Abandoned
Array ( [id] => 6392650 [patent_doc_number] => 20100163935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/639054 [patent_app_country] => US [patent_app_date] => 2009-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 35 [patent_no_of_words] => 17351 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20100163935.pdf [firstpage_image] =>[orig_patent_app_number] => 12639054 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/639054
Semiconductor device including normally-off type junction transistor and method of manufacturing the same Dec 15, 2009 Issued
Array ( [id] => 8760659 [patent_doc_number] => 08421182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Field effect transistor having MOS structure made of nitride compound semiconductor' [patent_app_type] => utility [patent_app_number] => 12/639199 [patent_app_country] => US [patent_app_date] => 2009-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4378 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12639199 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/639199
Field effect transistor having MOS structure made of nitride compound semiconductor Dec 15, 2009 Issued
Array ( [id] => 10857357 [patent_doc_number] => 08883554 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-11 [patent_title] => 'Method for manufacturing a semiconductor device using an oxide semiconductor' [patent_app_type] => utility [patent_app_number] => 12/639115 [patent_app_country] => US [patent_app_date] => 2009-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 48 [patent_no_of_words] => 19712 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12639115 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/639115
Method for manufacturing a semiconductor device using an oxide semiconductor Dec 15, 2009 Issued
Array ( [id] => 9074941 [patent_doc_number] => 08552521 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-08 [patent_title] => 'Semiconductor package to remove power noise using ground impedance' [patent_app_type] => utility [patent_app_number] => 12/639228 [patent_app_country] => US [patent_app_date] => 2009-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5617 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12639228 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/639228
Semiconductor package to remove power noise using ground impedance Dec 15, 2009 Issued
Array ( [id] => 6562524 [patent_doc_number] => 20100059824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'SYSTEM AND METHOD FOR I/O ESD PROTECTION WITH POLYSILICON REGIONS FABRICATED BY PROCESSES FOR MAKING CORE TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 12/623363 [patent_app_country] => US [patent_app_date] => 2009-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9262 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20100059824.pdf [firstpage_image] =>[orig_patent_app_number] => 12623363 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/623363
System and method for I/O ESD protection with polysilicon regions fabricated by processes for making core transistors Nov 19, 2009 Issued
Array ( [id] => 9711551 [patent_doc_number] => 08836127 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Interconnect with flexible dielectric layer' [patent_app_type] => utility [patent_app_number] => 12/621569 [patent_app_country] => US [patent_app_date] => 2009-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3830 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12621569 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/621569
Interconnect with flexible dielectric layer Nov 18, 2009 Issued
Array ( [id] => 11770335 [patent_doc_number] => 09379028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-28 [patent_title] => 'SOI CMOS structure having programmable floating backplate' [patent_app_type] => utility [patent_app_number] => 12/619285 [patent_app_country] => US [patent_app_date] => 2009-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7721 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12619285 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/619285
SOI CMOS structure having programmable floating backplate Nov 15, 2009 Issued
Array ( [id] => 6052347 [patent_doc_number] => 20110108954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'Growth of Planar Non-Polar M-Plane Gallium Nitride With Hydride Vapor Phase Epitaxy (HVPE)' [patent_app_type] => utility [patent_app_number] => 12/614313 [patent_app_country] => US [patent_app_date] => 2009-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2162 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20110108954.pdf [firstpage_image] =>[orig_patent_app_number] => 12614313 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/614313
Growth of planar non-polar {10-10} M-plane gallium nitride with hydride vapor phase epitaxy (HVPE) Nov 5, 2009 Issued
Array ( [id] => 6052391 [patent_doc_number] => 20110108974 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'POWER AND SIGNAL DISTRIBUTION OF INTEGRATED CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/613744 [patent_app_country] => US [patent_app_date] => 2009-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2738 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20110108974.pdf [firstpage_image] =>[orig_patent_app_number] => 12613744 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/613744
POWER AND SIGNAL DISTRIBUTION OF INTEGRATED CIRCUITS Nov 5, 2009 Abandoned
Array ( [id] => 6518103 [patent_doc_number] => 20100230722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'HIGH ELECTRON MOBILITY FIELD EFFECT TRANSISTOR (HEMT) DEVICE' [patent_app_type] => utility [patent_app_number] => 12/613168 [patent_app_country] => US [patent_app_date] => 2009-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2702 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20100230722.pdf [firstpage_image] =>[orig_patent_app_number] => 12613168 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/613168
HIGH ELECTRON MOBILITY FIELD EFFECT TRANSISTOR (HEMT) DEVICE Nov 4, 2009 Abandoned
Array ( [id] => 6400689 [patent_doc_number] => 20100148303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/613237 [patent_app_country] => US [patent_app_date] => 2009-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6582 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20100148303.pdf [firstpage_image] =>[orig_patent_app_number] => 12613237 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/613237
SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME Nov 4, 2009 Abandoned
Array ( [id] => 10892840 [patent_doc_number] => 08916452 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-23 [patent_title] => 'Semiconductor device and method of forming WLCSP using wafer sections containing multiple die' [patent_app_type] => utility [patent_app_number] => 12/612938 [patent_app_country] => US [patent_app_date] => 2009-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 40 [patent_no_of_words] => 7369 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12612938 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/612938
Semiconductor device and method of forming WLCSP using wafer sections containing multiple die Nov 4, 2009 Issued
Array ( [id] => 6447363 [patent_doc_number] => 20100038700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-18 [patent_title] => 'Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 12/580289 [patent_app_country] => US [patent_app_date] => 2009-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15973 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20100038700.pdf [firstpage_image] =>[orig_patent_app_number] => 12580289 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/580289
Semiconductor device with improved common source arrangement for adjacent non-volatile memory cells Oct 15, 2009 Issued
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