Search

Andrew M Falik

Examiner (ID: 2395)

Most Active Art Unit
2407
Art Unit(s)
3401, 3505, 3765, 3727, 3741, 2407, 3408, 2899
Total Applications
2593
Issued Applications
2494
Pending Applications
22
Abandoned Applications
77

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3932207 [patent_doc_number] => 05952724 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Semiconductor device incorporating a stepped contact hole' [patent_app_type] => 1 [patent_app_number] => 8/878947 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 6181 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/952/05952724.pdf [firstpage_image] =>[orig_patent_app_number] => 878947 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/878947
Semiconductor device incorporating a stepped contact hole Jun 18, 1997 Issued
Array ( [id] => 3775826 [patent_doc_number] => 05773856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Structure for connecting to integrated circuitry' [patent_app_type] => 1 [patent_app_number] => 8/878452 [patent_app_country] => US [patent_app_date] => 1997-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3878 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/773/05773856.pdf [firstpage_image] =>[orig_patent_app_number] => 878452 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/878452
Structure for connecting to integrated circuitry Jun 17, 1997 Issued
Array ( [id] => 4227878 [patent_doc_number] => 06011308 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Semiconductor device having a barrier film formed to prevent the entry of moisture and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/874359 [patent_app_country] => US [patent_app_date] => 1997-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 3094 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/011/06011308.pdf [firstpage_image] =>[orig_patent_app_number] => 874359 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/874359
Semiconductor device having a barrier film formed to prevent the entry of moisture and method of manufacturing the same Jun 12, 1997 Issued
Array ( [id] => 3990182 [patent_doc_number] => 05959362 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Device mounting a semiconductor element on a wiring substrate including an adhesive material having first and second adhesive components with different cure characteristics' [patent_app_type] => 1 [patent_app_number] => 8/874277 [patent_app_country] => US [patent_app_date] => 1997-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5929 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959362.pdf [firstpage_image] =>[orig_patent_app_number] => 874277 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/874277
Device mounting a semiconductor element on a wiring substrate including an adhesive material having first and second adhesive components with different cure characteristics Jun 12, 1997 Issued
Array ( [id] => 3940855 [patent_doc_number] => 05929529 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Reticle semiconductor wafer, and semiconductor chip' [patent_app_type] => 1 [patent_app_number] => 8/874713 [patent_app_country] => US [patent_app_date] => 1997-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3442 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/929/05929529.pdf [firstpage_image] =>[orig_patent_app_number] => 874713 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/874713
Reticle semiconductor wafer, and semiconductor chip Jun 12, 1997 Issued
Array ( [id] => 3845634 [patent_doc_number] => 05847468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Alignment mark for use in making semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/873563 [patent_app_country] => US [patent_app_date] => 1997-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 44 [patent_no_of_words] => 19632 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/847/05847468.pdf [firstpage_image] =>[orig_patent_app_number] => 873563 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/873563
Alignment mark for use in making semiconductor devices Jun 11, 1997 Issued
Array ( [id] => 3944374 [patent_doc_number] => 05973375 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Camouflaged circuit structure with step implants' [patent_app_type] => 1 [patent_app_number] => 8/869524 [patent_app_country] => US [patent_app_date] => 1997-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 5701 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973375.pdf [firstpage_image] =>[orig_patent_app_number] => 869524 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/869524
Camouflaged circuit structure with step implants Jun 5, 1997 Issued
Array ( [id] => 3984680 [patent_doc_number] => 05949098 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Semiconductor integrated circuit having an improved arrangement of power supply lines to reduce noise occurring therein' [patent_app_type] => 1 [patent_app_number] => 8/868474 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5338 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949098.pdf [firstpage_image] =>[orig_patent_app_number] => 868474 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/868474
Semiconductor integrated circuit having an improved arrangement of power supply lines to reduce noise occurring therein Jun 2, 1997 Issued
Array ( [id] => 4013495 [patent_doc_number] => 05889314 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Mixed-mode IC having an isolator for minimizing cross-talk through substrate and method of fabricating same' [patent_app_type] => 1 [patent_app_number] => 8/868259 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 2681 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889314.pdf [firstpage_image] =>[orig_patent_app_number] => 868259 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/868259
Mixed-mode IC having an isolator for minimizing cross-talk through substrate and method of fabricating same Jun 2, 1997 Issued
Array ( [id] => 4019718 [patent_doc_number] => 05880493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Semiconductor integrated circuit devices adapted for automatic design and method of arranging such devices' [patent_app_type] => 1 [patent_app_number] => 8/868046 [patent_app_country] => US [patent_app_date] => 1997-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 83 [patent_figures_cnt] => 114 [patent_no_of_words] => 39290 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/880/05880493.pdf [firstpage_image] =>[orig_patent_app_number] => 868046 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/868046
Semiconductor integrated circuit devices adapted for automatic design and method of arranging such devices Jun 2, 1997 Issued
Array ( [id] => 3998357 [patent_doc_number] => 05892266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Layout structure of capacitive element(s) and interconnections in a semiconductor' [patent_app_type] => 1 [patent_app_number] => 8/865442 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 1319 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892266.pdf [firstpage_image] =>[orig_patent_app_number] => 865442 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865442
Layout structure of capacitive element(s) and interconnections in a semiconductor May 29, 1997 Issued
Array ( [id] => 4070374 [patent_doc_number] => 06008510 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-28 [patent_title] => 'Silicon on insulator master slice semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/865328 [patent_app_country] => US [patent_app_date] => 1997-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 4315 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/008/06008510.pdf [firstpage_image] =>[orig_patent_app_number] => 865328 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865328
Silicon on insulator master slice semiconductor integrated circuit May 28, 1997 Issued
Array ( [id] => 3874643 [patent_doc_number] => 05838055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Trench sidewall patterned by vapor phase etching' [patent_app_type] => 1 [patent_app_number] => 8/865261 [patent_app_country] => US [patent_app_date] => 1997-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2950 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838055.pdf [firstpage_image] =>[orig_patent_app_number] => 865261 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865261
Trench sidewall patterned by vapor phase etching May 28, 1997 Issued
Array ( [id] => 3896062 [patent_doc_number] => 05834818 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Structure for making sub-lithographic images by the intersection of two spacers' [patent_app_type] => 1 [patent_app_number] => 8/864836 [patent_app_country] => US [patent_app_date] => 1997-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2446 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/834/05834818.pdf [firstpage_image] =>[orig_patent_app_number] => 864836 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/864836
Structure for making sub-lithographic images by the intersection of two spacers May 28, 1997 Issued
Array ( [id] => 3980351 [patent_doc_number] => 05917206 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Gate array system in which functional blocks are connected by fixed wiring' [patent_app_type] => 1 [patent_app_number] => 8/865326 [patent_app_country] => US [patent_app_date] => 1997-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6371 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917206.pdf [firstpage_image] =>[orig_patent_app_number] => 865326 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865326
Gate array system in which functional blocks are connected by fixed wiring May 28, 1997 Issued
Array ( [id] => 4210210 [patent_doc_number] => 06078095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Power transistor including a plurality of unit transistors' [patent_app_type] => 1 [patent_app_number] => 8/865049 [patent_app_country] => US [patent_app_date] => 1997-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4431 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078095.pdf [firstpage_image] =>[orig_patent_app_number] => 865049 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/865049
Power transistor including a plurality of unit transistors May 28, 1997 Issued
Array ( [id] => 3794584 [patent_doc_number] => 05841175 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Semiconductor device in which an increase in threshold voltage, resulting from back-gate bias effect is mitigated, and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/863601 [patent_app_country] => US [patent_app_date] => 1997-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 87 [patent_no_of_words] => 14508 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841175.pdf [firstpage_image] =>[orig_patent_app_number] => 863601 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/863601
Semiconductor device in which an increase in threshold voltage, resulting from back-gate bias effect is mitigated, and method of manufacturing the same May 26, 1997 Issued
Array ( [id] => 4103413 [patent_doc_number] => 06049135 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Bed structure underlying electrode pad of semiconductor device and method for manufacturing same' [patent_app_type] => 1 [patent_app_number] => 8/863423 [patent_app_country] => US [patent_app_date] => 1997-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 24 [patent_no_of_words] => 5094 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049135.pdf [firstpage_image] =>[orig_patent_app_number] => 863423 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/863423
Bed structure underlying electrode pad of semiconductor device and method for manufacturing same May 26, 1997 Issued
Array ( [id] => 4031378 [patent_doc_number] => 05903019 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Semiconductor device having a plurality of input/output cell areas with reduced pitches therebetween' [patent_app_type] => 1 [patent_app_number] => 8/859036 [patent_app_country] => US [patent_app_date] => 1997-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5097 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903019.pdf [firstpage_image] =>[orig_patent_app_number] => 859036 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/859036
Semiconductor device having a plurality of input/output cell areas with reduced pitches therebetween May 19, 1997 Issued
Array ( [id] => 3954729 [patent_doc_number] => 05955776 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Spherical shaped semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/858004 [patent_app_country] => US [patent_app_date] => 1997-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 27 [patent_no_of_words] => 8689 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/955/05955776.pdf [firstpage_image] =>[orig_patent_app_number] => 858004 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/858004
Spherical shaped semiconductor integrated circuit May 15, 1997 Issued
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