![](/images/general/no_picture/200_user.png)
Andrew M Falik
Examiner (ID: 2395)
Most Active Art Unit | 2407 |
Art Unit(s) | 3401, 3505, 3765, 3727, 3741, 2407, 3408, 2899 |
Total Applications | 2593 |
Issued Applications | 2494 |
Pending Applications | 22 |
Abandoned Applications | 77 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 4022249
[patent_doc_number] => 05907183
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-25
[patent_title] => 'Non-volatile semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 8/854434
[patent_app_country] => US
[patent_app_date] => 1997-05-12
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[pdf_file] => patents/05/907/05907183.pdf
[firstpage_image] =>[orig_patent_app_number] => 854434
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/854434 | Non-volatile semiconductor memory device | May 11, 1997 | Issued |
Array
(
[id] => 3780186
[patent_doc_number] => 05808338
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[patent_kind] => NA
[patent_issue_date] => 1998-09-15
[patent_title] => 'Nonvolatile semiconductor memory'
[patent_app_type] => 1
[patent_app_number] => 8/848396
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[patent_app_date] => 1997-05-08
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/848396 | Nonvolatile semiconductor memory | May 7, 1997 | Issued |
Array
(
[id] => 4212659
[patent_doc_number] => 06028361
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-22
[patent_title] => 'Method of manufacturing of semiconductor device having low leakage current'
[patent_app_type] => 1
[patent_app_number] => 8/852812
[patent_app_country] => US
[patent_app_date] => 1997-05-07
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/852812 | Method of manufacturing of semiconductor device having low leakage current | May 6, 1997 | Issued |
Array
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[patent_doc_number] => 05965942
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[patent_kind] => NA
[patent_issue_date] => 1999-10-12
[patent_title] => 'Semiconductor memory device with amorphous diffusion barrier between capacitor and plug'
[patent_app_type] => 1
[patent_app_number] => 8/851895
[patent_app_country] => US
[patent_app_date] => 1997-05-06
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/851895 | Semiconductor memory device with amorphous diffusion barrier between capacitor and plug | May 5, 1997 | Issued |
Array
(
[id] => 3748053
[patent_doc_number] => 05801421
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-01
[patent_title] => 'Staggered contact placement on CMOS chip'
[patent_app_type] => 1
[patent_app_number] => 8/850278
[patent_app_country] => US
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[firstpage_image] =>[orig_patent_app_number] => 850278
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/850278 | Staggered contact placement on CMOS chip | May 4, 1997 | Issued |
Array
(
[id] => 3903852
[patent_doc_number] => 05751046
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[patent_kind] => NA
[patent_issue_date] => 1998-05-12
[patent_title] => 'Semiconductor device with V.sub.T implant'
[patent_app_type] => 1
[patent_app_number] => 8/850950
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[firstpage_image] =>[orig_patent_app_number] => 850950
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/850950 | Semiconductor device with V.sub.T implant | May 4, 1997 | Issued |
Array
(
[id] => 4038494
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[patent_title] => 'Semiconductor fabrication employing a spacer metallization technique'
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[pdf_file] => patents/05/994/05994779.pdf
[firstpage_image] =>[orig_patent_app_number] => 850253
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/850253 | Semiconductor fabrication employing a spacer metallization technique | May 1, 1997 | Issued |
Array
(
[id] => 3926857
[patent_doc_number] => 05914516
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[patent_kind] => NA
[patent_issue_date] => 1999-06-22
[patent_title] => 'Buffer circuit with wide gate input transistor'
[patent_app_type] => 1
[patent_app_number] => 8/841642
[patent_app_country] => US
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[pdf_file] => patents/05/914/05914516.pdf
[firstpage_image] =>[orig_patent_app_number] => 841642
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/841642 | Buffer circuit with wide gate input transistor | Apr 29, 1997 | Issued |
Array
(
[id] => 4049019
[patent_doc_number] => 05874773
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-23
[patent_title] => 'Lead frame having a supporting pad with a plurality of slits arranged to permit the flow of resin so as to prevent the occurrence of voids'
[patent_app_type] => 1
[patent_app_number] => 8/841329
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/841329 | Lead frame having a supporting pad with a plurality of slits arranged to permit the flow of resin so as to prevent the occurrence of voids | Apr 29, 1997 | Issued |
Array
(
[id] => 4049121
[patent_doc_number] => 05912483
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-15
[patent_title] => 'Output circuit provided with source follower circuit having depletion type MOS transistor'
[patent_app_type] => 1
[patent_app_number] => 8/847675
[patent_app_country] => US
[patent_app_date] => 1997-04-28
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[pdf_file] => patents/05/912/05912483.pdf
[firstpage_image] =>[orig_patent_app_number] => 847675
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/847675 | Output circuit provided with source follower circuit having depletion type MOS transistor | Apr 27, 1997 | Issued |
Array
(
[id] => 3766285
[patent_doc_number] => 05844263
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-01
[patent_title] => 'Semiconductor integrated device having independent circuit blocks and a power breaking means for selectively supplying power to the circuit blocks'
[patent_app_type] => 1
[patent_app_number] => 8/837940
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/837940 | Semiconductor integrated device having independent circuit blocks and a power breaking means for selectively supplying power to the circuit blocks | Apr 27, 1997 | Issued |
Array
(
[id] => 3830279
[patent_doc_number] => 05731623
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-24
[patent_title] => 'Bipolar device with trench structure'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/845646 | Bipolar device with trench structure | Apr 24, 1997 | Issued |
Array
(
[id] => 3892289
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[patent_issue_date] => 1998-07-07
[patent_title] => 'Low profile variable width input/output cells'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/837570 | Low profile variable width input/output cells | Apr 20, 1997 | Issued |
Array
(
[id] => 3874195
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[firstpage_image] =>[orig_patent_app_number] => 840904
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/840904 | Semiconductor device and a method for manufacturing the same | Apr 16, 1997 | Issued |
Array
(
[id] => 3980472
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[patent_issue_date] => 1999-05-18
[patent_title] => 'Semiconductor device with high voltage protection'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/837344 | Semiconductor device with high voltage protection | Apr 16, 1997 | Issued |
Array
(
[id] => 3932098
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[patent_title] => 'Pin attach structure for an electronic package'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/842859 | Pin attach structure for an electronic package | Apr 15, 1997 | Issued |
Array
(
[id] => 3794541
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/833200 | SOI input protection circuit | Apr 13, 1997 | Issued |
Array
(
[id] => 3980308
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Array
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Array
(
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[patent_title] => 'Heterojunction field effect transistor having a InAlAs Schottky barrier layer formed upon an n-InP donor layer'
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[pdf_file] => patents/05/767/05767539.pdf
[firstpage_image] =>[orig_patent_app_number] => 826026
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/826026 | Heterojunction field effect transistor having a InAlAs Schottky barrier layer formed upon an n-InP donor layer | Mar 27, 1997 | Issued |