Search

Andrew M Falik

Examiner (ID: 2395)

Most Active Art Unit
2407
Art Unit(s)
3401, 3505, 3765, 3727, 3741, 2407, 3408, 2899
Total Applications
2593
Issued Applications
2494
Pending Applications
22
Abandoned Applications
77

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4022249 [patent_doc_number] => 05907183 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Non-volatile semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/854434 [patent_app_country] => US [patent_app_date] => 1997-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 22 [patent_no_of_words] => 5776 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907183.pdf [firstpage_image] =>[orig_patent_app_number] => 854434 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/854434
Non-volatile semiconductor memory device May 11, 1997 Issued
Array ( [id] => 3780186 [patent_doc_number] => 05808338 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Nonvolatile semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/848396 [patent_app_country] => US [patent_app_date] => 1997-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 11124 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/808/05808338.pdf [firstpage_image] =>[orig_patent_app_number] => 848396 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/848396
Nonvolatile semiconductor memory May 7, 1997 Issued
Array ( [id] => 4212659 [patent_doc_number] => 06028361 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Method of manufacturing of semiconductor device having low leakage current' [patent_app_type] => 1 [patent_app_number] => 8/852812 [patent_app_country] => US [patent_app_date] => 1997-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 65 [patent_no_of_words] => 7959 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028361.pdf [firstpage_image] =>[orig_patent_app_number] => 852812 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/852812
Method of manufacturing of semiconductor device having low leakage current May 6, 1997 Issued
Array ( [id] => 4080595 [patent_doc_number] => 05965942 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Semiconductor memory device with amorphous diffusion barrier between capacitor and plug' [patent_app_type] => 1 [patent_app_number] => 8/851895 [patent_app_country] => US [patent_app_date] => 1997-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3480 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/965/05965942.pdf [firstpage_image] =>[orig_patent_app_number] => 851895 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/851895
Semiconductor memory device with amorphous diffusion barrier between capacitor and plug May 5, 1997 Issued
Array ( [id] => 3748053 [patent_doc_number] => 05801421 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Staggered contact placement on CMOS chip' [patent_app_type] => 1 [patent_app_number] => 8/850278 [patent_app_country] => US [patent_app_date] => 1997-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2709 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801421.pdf [firstpage_image] =>[orig_patent_app_number] => 850278 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/850278
Staggered contact placement on CMOS chip May 4, 1997 Issued
Array ( [id] => 3903852 [patent_doc_number] => 05751046 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Semiconductor device with V.sub.T implant' [patent_app_type] => 1 [patent_app_number] => 8/850950 [patent_app_country] => US [patent_app_date] => 1997-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 5012 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751046.pdf [firstpage_image] =>[orig_patent_app_number] => 850950 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/850950
Semiconductor device with V.sub.T implant May 4, 1997 Issued
Array ( [id] => 4038494 [patent_doc_number] => 05994779 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Semiconductor fabrication employing a spacer metallization technique' [patent_app_type] => 1 [patent_app_number] => 8/850253 [patent_app_country] => US [patent_app_date] => 1997-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3752 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994779.pdf [firstpage_image] =>[orig_patent_app_number] => 850253 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/850253
Semiconductor fabrication employing a spacer metallization technique May 1, 1997 Issued
Array ( [id] => 3926857 [patent_doc_number] => 05914516 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-22 [patent_title] => 'Buffer circuit with wide gate input transistor' [patent_app_type] => 1 [patent_app_number] => 8/841642 [patent_app_country] => US [patent_app_date] => 1997-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4618 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/914/05914516.pdf [firstpage_image] =>[orig_patent_app_number] => 841642 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/841642
Buffer circuit with wide gate input transistor Apr 29, 1997 Issued
Array ( [id] => 4049019 [patent_doc_number] => 05874773 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Lead frame having a supporting pad with a plurality of slits arranged to permit the flow of resin so as to prevent the occurrence of voids' [patent_app_type] => 1 [patent_app_number] => 8/841329 [patent_app_country] => US [patent_app_date] => 1997-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 6466 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/874/05874773.pdf [firstpage_image] =>[orig_patent_app_number] => 841329 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/841329
Lead frame having a supporting pad with a plurality of slits arranged to permit the flow of resin so as to prevent the occurrence of voids Apr 29, 1997 Issued
Array ( [id] => 4049121 [patent_doc_number] => 05912483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Output circuit provided with source follower circuit having depletion type MOS transistor' [patent_app_type] => 1 [patent_app_number] => 8/847675 [patent_app_country] => US [patent_app_date] => 1997-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3558 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912483.pdf [firstpage_image] =>[orig_patent_app_number] => 847675 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/847675
Output circuit provided with source follower circuit having depletion type MOS transistor Apr 27, 1997 Issued
Array ( [id] => 3766285 [patent_doc_number] => 05844263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Semiconductor integrated device having independent circuit blocks and a power breaking means for selectively supplying power to the circuit blocks' [patent_app_type] => 1 [patent_app_number] => 8/837940 [patent_app_country] => US [patent_app_date] => 1997-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 2816 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844263.pdf [firstpage_image] =>[orig_patent_app_number] => 837940 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/837940
Semiconductor integrated device having independent circuit blocks and a power breaking means for selectively supplying power to the circuit blocks Apr 27, 1997 Issued
Array ( [id] => 3830279 [patent_doc_number] => 05731623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'Bipolar device with trench structure' [patent_app_type] => 1 [patent_app_number] => 8/845646 [patent_app_country] => US [patent_app_date] => 1997-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2749 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/731/05731623.pdf [firstpage_image] =>[orig_patent_app_number] => 845646 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/845646
Bipolar device with trench structure Apr 24, 1997 Issued
Array ( [id] => 3892289 [patent_doc_number] => 05777354 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Low profile variable width input/output cells' [patent_app_type] => 1 [patent_app_number] => 8/837570 [patent_app_country] => US [patent_app_date] => 1997-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3217 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/777/05777354.pdf [firstpage_image] =>[orig_patent_app_number] => 837570 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/837570
Low profile variable width input/output cells Apr 20, 1997 Issued
Array ( [id] => 3874195 [patent_doc_number] => 05838027 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Semiconductor device and a method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/840904 [patent_app_country] => US [patent_app_date] => 1997-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2061 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838027.pdf [firstpage_image] =>[orig_patent_app_number] => 840904 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/840904
Semiconductor device and a method for manufacturing the same Apr 16, 1997 Issued
Array ( [id] => 3980472 [patent_doc_number] => 05905287 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Semiconductor device with high voltage protection' [patent_app_type] => 1 [patent_app_number] => 8/837344 [patent_app_country] => US [patent_app_date] => 1997-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 5379 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905287.pdf [firstpage_image] =>[orig_patent_app_number] => 837344 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/837344
Semiconductor device with high voltage protection Apr 16, 1997 Issued
Array ( [id] => 3932098 [patent_doc_number] => 05952716 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Pin attach structure for an electronic package' [patent_app_type] => 1 [patent_app_number] => 8/842859 [patent_app_country] => US [patent_app_date] => 1997-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 4568 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/952/05952716.pdf [firstpage_image] =>[orig_patent_app_number] => 842859 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/842859
Pin attach structure for an electronic package Apr 15, 1997 Issued
Array ( [id] => 3794541 [patent_doc_number] => 05841172 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'SOI input protection circuit' [patent_app_type] => 1 [patent_app_number] => 8/833200 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 5707 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841172.pdf [firstpage_image] =>[orig_patent_app_number] => 833200 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/833200
SOI input protection circuit Apr 13, 1997 Issued
Array ( [id] => 3980308 [patent_doc_number] => 05917203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Lateral gate vertical drift region transistor' [patent_app_type] => 1 [patent_app_number] => 8/829072 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4010 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917203.pdf [firstpage_image] =>[orig_patent_app_number] => 829072 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829072
Lateral gate vertical drift region transistor Mar 30, 1997 Issued
Array ( [id] => 3874410 [patent_doc_number] => 05838040 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Nonvolatile reprogrammable interconnect cell with FN tunneling in sense' [patent_app_type] => 1 [patent_app_number] => 8/829374 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 2740 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838040.pdf [firstpage_image] =>[orig_patent_app_number] => 829374 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/829374
Nonvolatile reprogrammable interconnect cell with FN tunneling in sense Mar 30, 1997 Issued
Array ( [id] => 3857292 [patent_doc_number] => 05767539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Heterojunction field effect transistor having a InAlAs Schottky barrier layer formed upon an n-InP donor layer' [patent_app_type] => 1 [patent_app_number] => 8/826026 [patent_app_country] => US [patent_app_date] => 1997-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3953 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767539.pdf [firstpage_image] =>[orig_patent_app_number] => 826026 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/826026
Heterojunction field effect transistor having a InAlAs Schottky barrier layer formed upon an n-InP donor layer Mar 27, 1997 Issued
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