Search

Andrew M Falik

Examiner (ID: 2395)

Most Active Art Unit
2407
Art Unit(s)
3401, 3505, 3765, 3727, 3741, 2407, 3408, 2899
Total Applications
2593
Issued Applications
2494
Pending Applications
22
Abandoned Applications
77

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3745800 [patent_doc_number] => 05786608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-28 [patent_title] => 'Semiconductor chemical sensor device with specific heater structure' [patent_app_type] => 1 [patent_app_number] => 8/806816 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2689 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/786/05786608.pdf [firstpage_image] =>[orig_patent_app_number] => 806816 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/806816
Semiconductor chemical sensor device with specific heater structure Feb 25, 1997 Issued
Array ( [id] => 4244252 [patent_doc_number] => 06166438 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Ultrathin electronics using stacked layers and interconnect vias' [patent_app_type] => 1 [patent_app_number] => 8/816397 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 5645 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166438.pdf [firstpage_image] =>[orig_patent_app_number] => 816397 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/816397
Ultrathin electronics using stacked layers and interconnect vias Feb 25, 1997 Issued
Array ( [id] => 3834331 [patent_doc_number] => 05760439 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 8/806629 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2895 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/760/05760439.pdf [firstpage_image] =>[orig_patent_app_number] => 806629 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/806629
Semiconductor memory device Feb 25, 1997 Issued
Array ( [id] => 4038244 [patent_doc_number] => 05994761 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor' [patent_app_type] => 1 [patent_app_number] => 8/806436 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6440 [patent_no_of_claims] => 67 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/994/05994761.pdf [firstpage_image] =>[orig_patent_app_number] => 806436 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/806436
Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor Feb 25, 1997 Issued
Array ( [id] => 3788468 [patent_doc_number] => 05821594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Semiconductor device having a self-aligned type contact hole' [patent_app_type] => 1 [patent_app_number] => 8/805564 [patent_app_country] => US [patent_app_date] => 1997-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 32 [patent_no_of_words] => 7136 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/821/05821594.pdf [firstpage_image] =>[orig_patent_app_number] => 805564 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/805564
Semiconductor device having a self-aligned type contact hole Feb 24, 1997 Issued
Array ( [id] => 4062046 [patent_doc_number] => 05864154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Semiconductor memory device and method for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 8/804664 [patent_app_country] => US [patent_app_date] => 1997-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 46 [patent_no_of_words] => 7050 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/864/05864154.pdf [firstpage_image] =>[orig_patent_app_number] => 804664 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/804664
Semiconductor memory device and method for fabricating the same Feb 24, 1997 Issued
Array ( [id] => 4309744 [patent_doc_number] => 06188120 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Method and materials for through-mask electroplating and selective base removal' [patent_app_type] => 1 [patent_app_number] => 8/805403 [patent_app_country] => US [patent_app_date] => 1997-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 21 [patent_no_of_words] => 3368 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188120.pdf [firstpage_image] =>[orig_patent_app_number] => 805403 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/805403
Method and materials for through-mask electroplating and selective base removal Feb 23, 1997 Issued
Array ( [id] => 3998243 [patent_doc_number] => 05892256 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Semiconductor memory and a method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/804747 [patent_app_country] => US [patent_app_date] => 1997-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 34 [patent_no_of_words] => 7467 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892256.pdf [firstpage_image] =>[orig_patent_app_number] => 804747 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/804747
Semiconductor memory and a method of manufacturing the same Feb 20, 1997 Issued
Array ( [id] => 4041782 [patent_doc_number] => 05856691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-05 [patent_title] => 'Element-to-element interconnection in semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/802354 [patent_app_country] => US [patent_app_date] => 1997-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 33 [patent_no_of_words] => 9437 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/856/05856691.pdf [firstpage_image] =>[orig_patent_app_number] => 802354 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/802354
Element-to-element interconnection in semiconductor device Feb 20, 1997 Issued
Array ( [id] => 3799361 [patent_doc_number] => 05780894 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Nonvolatile semiconductor memory device having stacked-gate type transistor' [patent_app_type] => 1 [patent_app_number] => 8/802946 [patent_app_country] => US [patent_app_date] => 1997-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5987 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/780/05780894.pdf [firstpage_image] =>[orig_patent_app_number] => 802946 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/802946
Nonvolatile semiconductor memory device having stacked-gate type transistor Feb 20, 1997 Issued
Array ( [id] => 3834542 [patent_doc_number] => 05760451 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Raised source/drain with silicided contacts for semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/803098 [patent_app_country] => US [patent_app_date] => 1997-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2742 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/760/05760451.pdf [firstpage_image] =>[orig_patent_app_number] => 803098 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/803098
Raised source/drain with silicided contacts for semiconductor devices Feb 19, 1997 Issued
Array ( [id] => 3879149 [patent_doc_number] => 05763927 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'High-voltage lateral field effect transistor having auxiliary drain electrode for a step-down drain voltage' [patent_app_type] => 1 [patent_app_number] => 8/802312 [patent_app_country] => US [patent_app_date] => 1997-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5073 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/763/05763927.pdf [firstpage_image] =>[orig_patent_app_number] => 802312 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/802312
High-voltage lateral field effect transistor having auxiliary drain electrode for a step-down drain voltage Feb 17, 1997 Issued
Array ( [id] => 3944544 [patent_doc_number] => 05973386 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Semiconductor substrate having silicon oxide layers formed between polysilicon layers' [patent_app_type] => 1 [patent_app_number] => 8/800235 [patent_app_country] => US [patent_app_date] => 1997-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6512 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973386.pdf [firstpage_image] =>[orig_patent_app_number] => 800235 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/800235
Semiconductor substrate having silicon oxide layers formed between polysilicon layers Feb 11, 1997 Issued
Array ( [id] => 3853015 [patent_doc_number] => 05719446 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-17 [patent_title] => 'Multilayer interconnect structure for semiconductor device and method of manufacturing same' [patent_app_type] => 1 [patent_app_number] => 8/797925 [patent_app_country] => US [patent_app_date] => 1997-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 9376 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/719/05719446.pdf [firstpage_image] =>[orig_patent_app_number] => 797925 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/797925
Multilayer interconnect structure for semiconductor device and method of manufacturing same Feb 11, 1997 Issued
Array ( [id] => 3750657 [patent_doc_number] => 05717235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Non-volatile memory device having ferromagnetic and piezoelectric properties' [patent_app_type] => 1 [patent_app_number] => 8/797086 [patent_app_country] => US [patent_app_date] => 1997-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 7782 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717235.pdf [firstpage_image] =>[orig_patent_app_number] => 797086 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/797086
Non-volatile memory device having ferromagnetic and piezoelectric properties Feb 9, 1997 Issued
Array ( [id] => 4008135 [patent_doc_number] => 05923430 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Method for characterizing defects on semiconductor wafers' [patent_app_type] => 1 [patent_app_number] => 8/794673 [patent_app_country] => US [patent_app_date] => 1997-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 7001 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923430.pdf [firstpage_image] =>[orig_patent_app_number] => 794673 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/794673
Method for characterizing defects on semiconductor wafers Feb 2, 1997 Issued
Array ( [id] => 3980577 [patent_doc_number] => 05905294 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'High rated voltage semiconductor device with floating diffusion regions' [patent_app_type] => 1 [patent_app_number] => 8/787682 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 7405 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905294.pdf [firstpage_image] =>[orig_patent_app_number] => 787682 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/787682
High rated voltage semiconductor device with floating diffusion regions Jan 22, 1997 Issued
Array ( [id] => 3820691 [patent_doc_number] => 05789792 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Isolation trench structures protruding above a substrate surface' [patent_app_type] => 1 [patent_app_number] => 8/788732 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 52 [patent_no_of_words] => 10018 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/789/05789792.pdf [firstpage_image] =>[orig_patent_app_number] => 788732 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/788732
Isolation trench structures protruding above a substrate surface Jan 22, 1997 Issued
Array ( [id] => 3852754 [patent_doc_number] => 05719427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-17 [patent_title] => 'Avalanche-enhanced CMOS transistor for EPROM/EEPROM and ESD-protection structures' [patent_app_type] => 1 [patent_app_number] => 8/783626 [patent_app_country] => US [patent_app_date] => 1997-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 7081 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/719/05719427.pdf [firstpage_image] =>[orig_patent_app_number] => 783626 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/783626
Avalanche-enhanced CMOS transistor for EPROM/EEPROM and ESD-protection structures Jan 13, 1997 Issued
Array ( [id] => 3892245 [patent_doc_number] => 05777351 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Compression bonded type semiconductor element and semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/777007 [patent_app_country] => US [patent_app_date] => 1997-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5002 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/777/05777351.pdf [firstpage_image] =>[orig_patent_app_number] => 777007 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/777007
Compression bonded type semiconductor element and semiconductor device Jan 6, 1997 Issued
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