Search

Andrew Q. Tran

Examiner (ID: 7081)

Most Active Art Unit
2824
Art Unit(s)
2511, 2812, 2818, 2824, 2825, 2827
Total Applications
1878
Issued Applications
1746
Pending Applications
27
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11910965 [patent_doc_number] => 09779783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Latching current sensing amplifier for memory array' [patent_app_type] => utility [patent_app_number] => 14/744800 [patent_app_country] => US [patent_app_date] => 2015-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3164 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14744800 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/744800
Latching current sensing amplifier for memory array Jun 18, 2015 Issued
Array ( [id] => 11910998 [patent_doc_number] => 09779817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Boosting channels of memory cells to reduce program disturb' [patent_app_type] => utility [patent_app_number] => 14/740685 [patent_app_country] => US [patent_app_date] => 2015-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8682 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14740685 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/740685
Boosting channels of memory cells to reduce program disturb Jun 15, 2015 Issued
Array ( [id] => 11180479 [patent_doc_number] => 09412473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-09 [patent_title] => 'System and method of a novel redundancy scheme for OTP' [patent_app_type] => utility [patent_app_number] => 14/545775 [patent_app_country] => US [patent_app_date] => 2015-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 44 [patent_no_of_words] => 16581 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14545775 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/545775
System and method of a novel redundancy scheme for OTP Jun 15, 2015 Issued
Array ( [id] => 11687164 [patent_doc_number] => 09685214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-20 [patent_title] => 'Devices and methods for controlling magnetic anisotropy with localized biaxial strain in a piezoelectric substrate' [patent_app_type] => utility [patent_app_number] => 14/740147 [patent_app_country] => US [patent_app_date] => 2015-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 6531 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14740147 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/740147
Devices and methods for controlling magnetic anisotropy with localized biaxial strain in a piezoelectric substrate Jun 14, 2015 Issued
Array ( [id] => 11775875 [patent_doc_number] => 09384820 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-07-05 [patent_title] => 'Aligning calibration segments for increased availability of memory subsystem' [patent_app_type] => utility [patent_app_number] => 14/738119 [patent_app_country] => US [patent_app_date] => 2015-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2867 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14738119 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/738119
Aligning calibration segments for increased availability of memory subsystem Jun 11, 2015 Issued
Array ( [id] => 11791556 [patent_doc_number] => 09401196 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-07-26 [patent_title] => 'Dual mode ferroelectric random access memory (FRAM) cell apparatus and methods with imprinted read-only (RO) data' [patent_app_type] => utility [patent_app_number] => 14/737247 [patent_app_country] => US [patent_app_date] => 2015-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 9232 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14737247 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/737247
Dual mode ferroelectric random access memory (FRAM) cell apparatus and methods with imprinted read-only (RO) data Jun 10, 2015 Issued
Array ( [id] => 11925415 [patent_doc_number] => 09793000 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Nonvolatile memories having data input/output switches for reducing parasitic capacitance of bus channel' [patent_app_type] => utility [patent_app_number] => 14/736683 [patent_app_country] => US [patent_app_date] => 2015-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9567 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14736683 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/736683
Nonvolatile memories having data input/output switches for reducing parasitic capacitance of bus channel Jun 10, 2015 Issued
Array ( [id] => 10659342 [patent_doc_number] => 20160005486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-01-07 [patent_title] => 'SENSE AMPLIFIER FOR A MEMORY CELL WITH A FAST SENSING SPEED' [patent_app_type] => utility [patent_app_number] => 14/736271 [patent_app_country] => US [patent_app_date] => 2015-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7937 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14736271 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/736271
Sense amplifier for a memory cell with a fast sensing speed Jun 10, 2015 Issued
Array ( [id] => 10384964 [patent_doc_number] => 20150269971 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-09-24 [patent_title] => 'METHOD FOR READING A THIRD-DIMENSIONAL EMBEDDED RE-WRITEABLE NON-VOLATILE MEMORY AND REGISTERS' [patent_app_type] => utility [patent_app_number] => 14/730173 [patent_app_country] => US [patent_app_date] => 2015-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3805 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14730173 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/730173
METHOD FOR READING A THIRD-DIMENSIONAL EMBEDDED RE-WRITEABLE NON-VOLATILE MEMORY AND REGISTERS Jun 2, 2015 Abandoned
Array ( [id] => 12256770 [patent_doc_number] => 09928919 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-27 [patent_title] => 'Method and apparatus for staggered start-up of a predefined, random, or dynamic number of flash memory devices' [patent_app_type] => utility [patent_app_number] => 14/716719 [patent_app_country] => US [patent_app_date] => 2015-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5292 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14716719 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/716719
Method and apparatus for staggered start-up of a predefined, random, or dynamic number of flash memory devices May 18, 2015 Issued
Array ( [id] => 11180441 [patent_doc_number] => 09412435 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-09 [patent_title] => 'Pipeline-controlled semiconductor memory device with reduced power consumption and memory access time' [patent_app_type] => utility [patent_app_number] => 14/699027 [patent_app_country] => US [patent_app_date] => 2015-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 47 [patent_no_of_words] => 21336 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14699027 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/699027
Pipeline-controlled semiconductor memory device with reduced power consumption and memory access time Apr 28, 2015 Issued
Array ( [id] => 10195584 [patent_doc_number] => 09224497 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-29 [patent_title] => 'One time programmable memory cell capable of reducing leakage current and preventing slow bit response' [patent_app_type] => utility [patent_app_number] => 14/697652 [patent_app_country] => US [patent_app_date] => 2015-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4211 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14697652 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/697652
One time programmable memory cell capable of reducing leakage current and preventing slow bit response Apr 27, 2015 Issued
Array ( [id] => 11096280 [patent_doc_number] => 20160293248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'STATIC RANDOM ACCESS MEMORY AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/696795 [patent_app_country] => US [patent_app_date] => 2015-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10374 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14696795 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/696795
Static random access memory (SRAM) with recovery circuit for a write operation Apr 26, 2015 Issued
Array ( [id] => 12202224 [patent_doc_number] => 09905297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-27 [patent_title] => 'Hybrid volatile and non-volatile memory device having a programmable register for shadowed storage locations' [patent_app_type] => utility [patent_app_number] => 14/697182 [patent_app_country] => US [patent_app_date] => 2015-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 6395 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14697182 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/697182
Hybrid volatile and non-volatile memory device having a programmable register for shadowed storage locations Apr 26, 2015 Issued
Array ( [id] => 10984006 [patent_doc_number] => 20160180950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'LOW VOLTAGE DETECTION CIRCUIT, NONVOLATILE MEMORY APPARATUS INCLUDING THE SAME, AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/694543 [patent_app_country] => US [patent_app_date] => 2015-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4417 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14694543 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/694543
Low voltage detection circuit, nonvolatile memory apparatus including the same, and operating method thereof Apr 22, 2015 Issued
Array ( [id] => 10984006 [patent_doc_number] => 20160180950 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'LOW VOLTAGE DETECTION CIRCUIT, NONVOLATILE MEMORY APPARATUS INCLUDING THE SAME, AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/694543 [patent_app_country] => US [patent_app_date] => 2015-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4417 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14694543 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/694543
Low voltage detection circuit, nonvolatile memory apparatus including the same, and operating method thereof Apr 22, 2015 Issued
Array ( [id] => 10563280 [patent_doc_number] => 09286961 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-03-15 [patent_title] => 'Memory controller half-clock delay adjustment' [patent_app_type] => utility [patent_app_number] => 14/672412 [patent_app_country] => US [patent_app_date] => 2015-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5918 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14672412 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/672412
Memory controller half-clock delay adjustment Mar 29, 2015 Issued
Array ( [id] => 11207663 [patent_doc_number] => 09437293 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-09-06 [patent_title] => 'Integrated setback read with reduced snapback disturb' [patent_app_type] => utility [patent_app_number] => 14/671471 [patent_app_country] => US [patent_app_date] => 2015-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 8005 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14671471 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/671471
Integrated setback read with reduced snapback disturb Mar 26, 2015 Issued
Array ( [id] => 10817200 [patent_doc_number] => 20160163362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-09 [patent_title] => 'INPUT CIRCUIT OF SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/634167 [patent_app_country] => US [patent_app_date] => 2015-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14634167 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/634167
Input circuit of three-dimensional semiconductor apparatus capable of enabling testing and direct access Feb 26, 2015 Issued
Array ( [id] => 11681117 [patent_doc_number] => 09679651 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-06-13 [patent_title] => 'Semiconductor memory device capable of determining an initial program condition for different memory cells' [patent_app_type] => utility [patent_app_number] => 14/633033 [patent_app_country] => US [patent_app_date] => 2015-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 38 [patent_no_of_words] => 22281 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14633033 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/633033
Semiconductor memory device capable of determining an initial program condition for different memory cells Feb 25, 2015 Issued
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