Search

Andrew Q. Tran

Examiner (ID: 7081)

Most Active Art Unit
2824
Art Unit(s)
2511, 2812, 2818, 2824, 2825, 2827
Total Applications
1878
Issued Applications
1746
Pending Applications
27
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10638227 [patent_doc_number] => 09355735 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-31 [patent_title] => 'Data recovery in a 3D memory device with a short circuit between word lines' [patent_app_type] => utility [patent_app_number] => 14/627575 [patent_app_country] => US [patent_app_date] => 2015-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 33 [patent_no_of_words] => 15213 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14627575 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/627575
Data recovery in a 3D memory device with a short circuit between word lines Feb 19, 2015 Issued
Array ( [id] => 10246400 [patent_doc_number] => 20150131395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-14 [patent_title] => 'Method for triggering a delay-locked loop (DLL) update operation or an impedance calibration operation in a dynamic random access memory device' [patent_app_type] => utility [patent_app_number] => 14/605724 [patent_app_country] => US [patent_app_date] => 2015-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7494 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14605724 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/605724
Method for triggering a delay-locked loop (DLL) update operation or an impedance calibration operation in a dynamic random access memory device Jan 25, 2015 Issued
Array ( [id] => 10066496 [patent_doc_number] => 09105352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-11 [patent_title] => 'Semiconductor storage apparatus with different number of sense amplifier PMOS driver transistors and NMOS driver transistors' [patent_app_type] => utility [patent_app_number] => 14/589782 [patent_app_country] => US [patent_app_date] => 2015-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 14271 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14589782 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/589782
Semiconductor storage apparatus with different number of sense amplifier PMOS driver transistors and NMOS driver transistors Jan 4, 2015 Issued
Array ( [id] => 10200597 [patent_doc_number] => 20150085583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'NONVOLATILE MEMORY APPARATUS, PROGRAM METHOD THEREOF, AND DATA PROCESSING SYSTEM USING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/557044 [patent_app_country] => US [patent_app_date] => 2014-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3375 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14557044 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/557044
NONVOLATILE MEMORY APPARATUS, PROGRAM METHOD THEREOF, AND DATA PROCESSING SYSTEM USING THE SAME Nov 30, 2014 Abandoned
Array ( [id] => 10200586 [patent_doc_number] => 20150085572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'STORAGE OF READ THRESHOLDS FOR NAND FLASH STORAGE USING LINEAR APPROXIMATION' [patent_app_type] => utility [patent_app_number] => 14/553745 [patent_app_country] => US [patent_app_date] => 2014-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6863 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14553745 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/553745
Storage of read thresholds for NAND flash storage using linear approximation Nov 24, 2014 Issued
Array ( [id] => 10502240 [patent_doc_number] => 09230643 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Verify or read pulse for phase change memory and switch' [patent_app_type] => utility [patent_app_number] => 14/528976 [patent_app_country] => US [patent_app_date] => 2014-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 7150 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14528976 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/528976
Verify or read pulse for phase change memory and switch Oct 29, 2014 Issued
Array ( [id] => 10717939 [patent_doc_number] => 20160064086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'CIRCUIT AND METHOD FOR ADJUSTING SELECT GATE VOLTAGE OF NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/471769 [patent_app_country] => US [patent_app_date] => 2014-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3709 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14471769 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/471769
Circuit for adjusting a select gate voltage of a non-volatile memory during erasure of memory cells based on a well voltage Aug 27, 2014 Issued
Array ( [id] => 10512649 [patent_doc_number] => 09240228 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-01-19 [patent_title] => 'Static memory apparatus and data reading method thereof' [patent_app_type] => utility [patent_app_number] => 14/457125 [patent_app_country] => US [patent_app_date] => 2014-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 3810 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14457125 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/457125
Static memory apparatus and data reading method thereof Aug 11, 2014 Issued
Array ( [id] => 10003844 [patent_doc_number] => 09047942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-02 [patent_title] => 'Non-transitory computer-readable media describing a hybrid volatile and non-volatile memory device with an overlapping region of addressable range of storage cells' [patent_app_type] => utility [patent_app_number] => 14/458212 [patent_app_country] => US [patent_app_date] => 2014-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 6368 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14458212 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/458212
Non-transitory computer-readable media describing a hybrid volatile and non-volatile memory device with an overlapping region of addressable range of storage cells Aug 11, 2014 Issued
Array ( [id] => 11781918 [patent_doc_number] => 09391120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-07-12 [patent_title] => 'Semiconductor memory device having unequal pitch vertical channel transistors used as selection transistors' [patent_app_type] => utility [patent_app_number] => 14/449417 [patent_app_country] => US [patent_app_date] => 2014-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 122 [patent_no_of_words] => 17910 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14449417 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/449417
Semiconductor memory device having unequal pitch vertical channel transistors used as selection transistors Jul 31, 2014 Issued
Array ( [id] => 9856428 [patent_doc_number] => 20150036445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-05 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/447287 [patent_app_country] => US [patent_app_date] => 2014-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6761 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14447287 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/447287
Semiconductor memory device including refresh operations having first and second cycles Jul 29, 2014 Issued
Array ( [id] => 10151916 [patent_doc_number] => 09184212 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-10 [patent_title] => 'Shift-register like magnetic storage memory and method for driving the same' [patent_app_type] => utility [patent_app_number] => 14/341059 [patent_app_country] => US [patent_app_date] => 2014-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 40 [patent_no_of_words] => 17850 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14341059 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/341059
Shift-register like magnetic storage memory and method for driving the same Jul 24, 2014 Issued
Array ( [id] => 10171840 [patent_doc_number] => 09202553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-01 [patent_title] => 'Semiconductor storage device' [patent_app_type] => utility [patent_app_number] => 14/332219 [patent_app_country] => US [patent_app_date] => 2014-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 11354 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14332219 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/332219
Semiconductor storage device Jul 14, 2014 Issued
Array ( [id] => 11770094 [patent_doc_number] => 09378779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-28 [patent_title] => 'System and method for automatic detection of power up for a dual-rail circuit' [patent_app_type] => utility [patent_app_number] => 14/329747 [patent_app_country] => US [patent_app_date] => 2014-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 5953 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14329747 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/329747
System and method for automatic detection of power up for a dual-rail circuit Jul 10, 2014 Issued
Array ( [id] => 10809520 [patent_doc_number] => 20160155679 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'ELECTRONIC HARDWARE ASSEMBLY' [patent_app_type] => utility [patent_app_number] => 14/899406 [patent_app_country] => US [patent_app_date] => 2014-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4927 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14899406 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/899406
Tamper resistant electronic hardware assembly with a non-functional die used as a protective layer Jun 26, 2014 Issued
Array ( [id] => 11578445 [patent_doc_number] => 09633714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Methods for bias sensing in DRAM sense amplifiers through voltage-coupling/decoupling devices' [patent_app_type] => utility [patent_app_number] => 14/316368 [patent_app_country] => US [patent_app_date] => 2014-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7489 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14316368 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/316368
Methods for bias sensing in DRAM sense amplifiers through voltage-coupling/decoupling devices Jun 25, 2014 Issued
Array ( [id] => 13946899 [patent_doc_number] => 10209215 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-19 [patent_title] => Integrated circuit sensor device for charge detection hybridizing a lateral metal oxide semiconductor field effect transistor (MOSFET) and a vertical bipolar junction transistor (BJT) [patent_app_type] => utility [patent_app_number] => 14/899428 [patent_app_country] => US [patent_app_date] => 2014-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6578 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14899428 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/899428
Integrated circuit sensor device for charge detection hybridizing a lateral metal oxide semiconductor field effect transistor (MOSFET) and a vertical bipolar junction transistor (BJT) Jun 16, 2014 Issued
Array ( [id] => 10795115 [patent_doc_number] => 20160141272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 14/899514 [patent_app_country] => US [patent_app_date] => 2014-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4495 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14899514 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/899514
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME Jun 4, 2014 Abandoned
Array ( [id] => 10086055 [patent_doc_number] => 09123406 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-01 [patent_title] => 'Semiconductor memory device capable of selectively enabling/disabling a first input unit and a second input unit in response to a first and second internal clock in a gear-down mode' [patent_app_type] => utility [patent_app_number] => 14/293649 [patent_app_country] => US [patent_app_date] => 2014-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 15817 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14293649 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/293649
Semiconductor memory device capable of selectively enabling/disabling a first input unit and a second input unit in response to a first and second internal clock in a gear-down mode Jun 1, 2014 Issued
Array ( [id] => 9718594 [patent_doc_number] => 20140254292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'OVERLAPPING INTERCONNECT SIGNAL LINES FOR REDUCING CAPACITIVE COUPLING EFFECTS' [patent_app_type] => utility [patent_app_number] => 14/287890 [patent_app_country] => US [patent_app_date] => 2014-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8964 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14287890 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/287890
Method of overlapping interconnect signal lines for reducing capacitive coupling effects May 26, 2014 Issued
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