| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 9939120
[patent_doc_number] => 08988939
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-03-24
[patent_title] => 'Pre-charge during programming for 3D memory using gate-induced drain leakage'
[patent_app_type] => utility
[patent_app_number] => 14/278351
[patent_app_country] => US
[patent_app_date] => 2014-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 27
[patent_no_of_words] => 12630
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 455
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14278351
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/278351 | Pre-charge during programming for 3D memory using gate-induced drain leakage | May 14, 2014 | Issued |
Array
(
[id] => 10336349
[patent_doc_number] => 20150221353
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-08-06
[patent_title] => 'DATA SENSING CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/277207
[patent_app_country] => US
[patent_app_date] => 2014-05-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 5054
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14277207
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/277207 | DATA SENSING CIRCUIT AND SEMICONDUCTOR APPARATUS USING THE SAME | May 13, 2014 | Abandoned |
Array
(
[id] => 10846098
[patent_doc_number] => 08873288
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-10-28
[patent_title] => 'Simultaneous sensing of multiple wordlines and detection of NAND failures'
[patent_app_type] => utility
[patent_app_number] => 14/257211
[patent_app_country] => US
[patent_app_date] => 2014-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 52
[patent_no_of_words] => 31174
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14257211
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/257211 | Simultaneous sensing of multiple wordlines and detection of NAND failures | Apr 20, 2014 | Issued |
Array
(
[id] => 9655411
[patent_doc_number] => 20140226416
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-08-14
[patent_title] => 'Erase Operation With Controlled Select Gate Voltage For 3D Non-Volatile Memory'
[patent_app_type] => utility
[patent_app_number] => 14/254586
[patent_app_country] => US
[patent_app_date] => 2014-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 13196
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14254586
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/254586 | Erase operation with controlled select gate voltage for 3D non-volatile memory | Apr 15, 2014 | Issued |
Array
(
[id] => 11187339
[patent_doc_number] => 09418747
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-08-16
[patent_title] => 'Nonvolatile memory device maintaining a bitline precharge during program verification periods for multi-level memory cells and related programming method'
[patent_app_type] => utility
[patent_app_number] => 14/227314
[patent_app_country] => US
[patent_app_date] => 2014-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 16
[patent_no_of_words] => 6855
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14227314
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/227314 | Nonvolatile memory device maintaining a bitline precharge during program verification periods for multi-level memory cells and related programming method | Mar 26, 2014 | Issued |
Array
(
[id] => 9863251
[patent_doc_number] => 20150043270
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-02-12
[patent_title] => 'MEMORY CELL HAVING BUILT-IN WRITE ASSIST'
[patent_app_type] => utility
[patent_app_number] => 14/227132
[patent_app_country] => US
[patent_app_date] => 2014-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 11263
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14227132
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/227132 | MEMORY CELL HAVING BUILT-IN WRITE ASSIST | Mar 26, 2014 | Abandoned |
Array
(
[id] => 10066492
[patent_doc_number] => 09105348
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-08-11
[patent_title] => 'Electronic device with a power supply circuit for controlling the operations of a non-volatile memory and a volatile memory therein'
[patent_app_type] => utility
[patent_app_number] => 14/227786
[patent_app_country] => US
[patent_app_date] => 2014-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4614
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14227786
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/227786 | Electronic device with a power supply circuit for controlling the operations of a non-volatile memory and a volatile memory therein | Mar 26, 2014 | Issued |
Array
(
[id] => 10846100
[patent_doc_number] => 08873290
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-10-28
[patent_title] => 'Non-volatile memory device capable of multi-page programming by simultaneously activating a plurality of selection lines based on programmed data'
[patent_app_type] => utility
[patent_app_number] => 14/225601
[patent_app_country] => US
[patent_app_date] => 2014-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 42
[patent_figures_cnt] => 45
[patent_no_of_words] => 17072
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14225601
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/225601 | Non-volatile memory device capable of multi-page programming by simultaneously activating a plurality of selection lines based on programmed data | Mar 25, 2014 | Issued |
Array
(
[id] => 9770028
[patent_doc_number] => 20140293690
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-10-02
[patent_title] => 'ELECTRONIC DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/226444
[patent_app_country] => US
[patent_app_date] => 2014-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4514
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14226444
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/226444 | Electronic device with a register for controlling the operations of a non-volatile memory and a volatile memory therein | Mar 25, 2014 | Issued |
Array
(
[id] => 10502257
[patent_doc_number] => 09230659
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-01-05
[patent_title] => 'Nonvolatile memory device capable of reducing a setup/precharge speed of a bitline for reducing peak current and related programming method'
[patent_app_type] => utility
[patent_app_number] => 14/223368
[patent_app_country] => US
[patent_app_date] => 2014-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 20
[patent_no_of_words] => 10575
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14223368
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/223368 | Nonvolatile memory device capable of reducing a setup/precharge speed of a bitline for reducing peak current and related programming method | Mar 23, 2014 | Issued |
Array
(
[id] => 10937933
[patent_doc_number] => 20140340955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-11-20
[patent_title] => 'ONE TIME PROGRAMABLE MEMORY CELL AND METHOD FOR PROGRAMING AND READING A MEMORY ARRAY COMPRISING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/222684
[patent_app_country] => US
[patent_app_date] => 2014-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 4082
[patent_no_of_claims] => 39
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14222684
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/222684 | One time programmable memory cell capable of reducing leakage current and preventing slow bit response | Mar 23, 2014 | Issued |
Array
(
[id] => 9755412
[patent_doc_number] => 20140286112
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-25
[patent_title] => 'SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/223928
[patent_app_country] => US
[patent_app_date] => 2014-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 24
[patent_figures_cnt] => 24
[patent_no_of_words] => 19331
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14223928
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/223928 | Semiconductor device capable of performing a read leveling and a write leveling based on an ambient temperature | Mar 23, 2014 | Issued |
Array
(
[id] => 10040341
[patent_doc_number] => 09081042
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-07-14
[patent_title] => 'Resistive memory element sensing using averaging'
[patent_app_type] => utility
[patent_app_number] => 14/221719
[patent_app_country] => US
[patent_app_date] => 2014-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 3756
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14221719
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/221719 | Resistive memory element sensing using averaging | Mar 20, 2014 | Issued |
Array
(
[id] => 11739966
[patent_doc_number] => 09704557
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-07-11
[patent_title] => 'Method and apparatus for storing retention time profile information based on retention time and temperature'
[patent_app_type] => utility
[patent_app_number] => 14/220862
[patent_app_country] => US
[patent_app_date] => 2014-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 9723
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 243
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14220862
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/220862 | Method and apparatus for storing retention time profile information based on retention time and temperature | Mar 19, 2014 | Issued |
Array
(
[id] => 10047203
[patent_doc_number] => 09087602
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-07-21
[patent_title] => 'Volatile memory device capable of relieving disturbances of adjacent memory cells and refresh method thereof'
[patent_app_type] => utility
[patent_app_number] => 14/219374
[patent_app_country] => US
[patent_app_date] => 2014-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 26
[patent_no_of_words] => 17900
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14219374
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/219374 | Volatile memory device capable of relieving disturbances of adjacent memory cells and refresh method thereof | Mar 18, 2014 | Issued |
Array
(
[id] => 10232139
[patent_doc_number] => 20150117133
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-04-30
[patent_title] => 'Semiconductor memory device capable of preventing degradation of memory cells and method for erasing the same'
[patent_app_type] => utility
[patent_app_number] => 14/219811
[patent_app_country] => US
[patent_app_date] => 2014-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7737
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14219811
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/219811 | Semiconductor memory device capable of preventing degradation of memory cells and method for erasing the same | Mar 18, 2014 | Issued |
Array
(
[id] => 9755373
[patent_doc_number] => 20140286073
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-25
[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/218058
[patent_app_country] => US
[patent_app_date] => 2014-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 23895
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14218058
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/218058 | Semiconductor device including a transistor with an oxide semiconductor film channel coupled to a capacitor | Mar 17, 2014 | Issued |
Array
(
[id] => 9733298
[patent_doc_number] => 20140269007
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2014-09-18
[patent_title] => 'COMPLEMENTARY METAL OXIDE OR METAL NITRIDE HETEROJUNCTION MEMORY DEVICES WITH ASYMMETRIC HYSTERESIS PROPERTY'
[patent_app_type] => utility
[patent_app_number] => 14/214478
[patent_app_country] => US
[patent_app_date] => 2014-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
[patent_figures_cnt] => 23
[patent_no_of_words] => 8705
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14214478
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/214478 | COMPLEMENTARY METAL OXIDE OR METAL NITRIDE HETEROJUNCTION MEMORY DEVICES WITH ASYMMETRIC HYSTERESIS PROPERTY | Mar 13, 2014 | Abandoned |
Array
(
[id] => 10377668
[patent_doc_number] => 20150262675
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2015-09-17
[patent_title] => 'Incremental step pulse programming (ISPP) scheme capable of determining a next starting pulse based on a current program-verify pulse for improving programming speed'
[patent_app_type] => utility
[patent_app_number] => 14/210063
[patent_app_country] => US
[patent_app_date] => 2014-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6928
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14210063
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/210063 | Incremental step pulse programming (ISPP) scheme capable of determining a next starting pulse based on a current program-verify pulse for improving programming speed | Mar 12, 2014 | Issued |
Array
(
[id] => 10066500
[patent_doc_number] => 09105357
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2015-08-11
[patent_title] => 'Semiconductor memory device and defective judging method thereof'
[patent_app_type] => utility
[patent_app_number] => 14/204165
[patent_app_country] => US
[patent_app_date] => 2014-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 21
[patent_no_of_words] => 7039
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14204165
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/204165 | Semiconductor memory device and defective judging method thereof | Mar 10, 2014 | Issued |