Andrew Q. Tran

Array ( [id] => 9595921 [patent_doc_number] => 20140192598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-10 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/205061 [patent_app_country] => US [patent_app_date] => 2014-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 9309 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14205061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9915795 [patent_doc_number] => 20150071001 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-12 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/204565 [patent_app_country] => US [patent_app_date] => 2014-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3905 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14204565 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9894350 [patent_doc_number] => 20150049549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-19 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER, AND MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/189929 [patent_app_country] => US [patent_app_date] => 2014-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 13845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14189929 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10207507 [patent_doc_number] => 20150092495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 14/186665 [patent_app_country] => US [patent_app_date] => 2014-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4090 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14186665 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10099679 [patent_doc_number] => 09135994 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Nonvolatile memory device having read circuits for performing Read-While-Write (RWW) operation and Read-Modify-Write (RMW) operation' [patent_app_type] => utility [patent_app_number] => 14/171873 [patent_app_country] => US [patent_app_date] => 2014-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 7726 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14171873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10053267 [patent_doc_number] => 09093146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-28 [patent_title] => 'Nonvolatile memory device and related method for reducing access latency' [patent_app_type] => utility [patent_app_number] => 14/171849 [patent_app_country] => US [patent_app_date] => 2014-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 6837 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14171849 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11453001 [patent_doc_number] => 09576650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Read measurement of a plurality of resistive memory cells for alleviating resistance and current drift' [patent_app_type] => utility [patent_app_number] => 14/164725 [patent_app_country] => US [patent_app_date] => 2014-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 5750 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14164725 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10321578 [patent_doc_number] => 20150206582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/157605 [patent_app_country] => US [patent_app_date] => 2014-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 14576 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14157605 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11411982 [patent_doc_number] => 09559298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Semiconductor memory with a multi-layer passivation layer formed over sidewalls of a variable resistance element' [patent_app_type] => utility [patent_app_number] => 14/157505 [patent_app_country] => US [patent_app_date] => 2014-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 11708 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14157505 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10207518 [patent_doc_number] => 20150092506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-02 [patent_title] => 'METHOD AND APPARATUS FOR TESTING MEMORY' [patent_app_type] => utility [patent_app_number] => 14/150783 [patent_app_country] => US [patent_app_date] => 2014-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3351 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14150783 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9447976 [patent_doc_number] => 20140119145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'SEMICONDUCTOR MEMORY INTEGRATED DEVICE HAVING A PRECHARGE CIRCUIT WITH THIN-FILM TRANSISTORS GATED BY A VOLTAGE HIGHER THAN A POWER SUPPLY VOLTAGE' [patent_app_type] => utility [patent_app_number] => 14/147166 [patent_app_country] => US [patent_app_date] => 2014-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9102 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14147166 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9846027 [patent_doc_number] => 08947954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-03 [patent_title] => 'Random access memory for use in an emulation environment' [patent_app_type] => utility [patent_app_number] => 14/145677 [patent_app_country] => US [patent_app_date] => 2013-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 3899 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14145677 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10624231 [patent_doc_number] => 09343180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-17 [patent_title] => 'Switched interface for stacked-die memory architecture with redundancy for substituting defective memory cells' [patent_app_type] => utility [patent_app_number] => 14/142565 [patent_app_country] => US [patent_app_date] => 2013-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7554 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14142565 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9395281 [patent_doc_number] => 20140092687 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'METHOD, APPARATUS, AND MANUFACTURE FOR STAGGERED START FOR MEMORY MODULE' [patent_app_type] => utility [patent_app_number] => 14/099340 [patent_app_country] => US [patent_app_date] => 2013-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5284 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14099340 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9368975 [patent_doc_number] => 20140078848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-20 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE, MEMORY CONTROLLER, AND DATA PROCESSING SYSTEM INCLUDING THESE' [patent_app_type] => utility [patent_app_number] => 14/085440 [patent_app_country] => US [patent_app_date] => 2013-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 16916 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14085440 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9361895 [patent_doc_number] => 20140071768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-13 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/079682 [patent_app_country] => US [patent_app_date] => 2013-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 18650 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14079682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9856413 [patent_doc_number] => 20150036429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-05 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/074310 [patent_app_country] => US [patent_app_date] => 2013-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7796 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14074310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9475789 [patent_doc_number] => 20140133252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'PARALLEL-SERIAL CONVERSION CIRCUIT, INTERFACE CIRCUIT, AND CONTROL DEVICE' [patent_app_type] => utility [patent_app_number] => 14/073662 [patent_app_country] => US [patent_app_date] => 2013-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 17058 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14073662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10200606 [patent_doc_number] => 20150085592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-26 [patent_title] => 'Bit-Line Discharge Assistance in Memory Devices' [patent_app_type] => utility [patent_app_number] => 14/070836 [patent_app_country] => US [patent_app_date] => 2013-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4987 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14070836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10925083 [patent_doc_number] => 20140328104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-06 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/071230 [patent_app_country] => US [patent_app_date] => 2013-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6298 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14071230 [rel_patent_id] =>[rel_patent_doc_number] =>)