Search

Andrew Q. Tran

Examiner (ID: 7081)

Most Active Art Unit
2824
Art Unit(s)
2511, 2812, 2818, 2824, 2825, 2827
Total Applications
1878
Issued Applications
1746
Pending Applications
27
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10022054 [patent_doc_number] => 09064546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-23 [patent_title] => 'Memory device selecting different column selection lines based on different offset values and memory system including the same' [patent_app_type] => utility [patent_app_number] => 14/069188 [patent_app_country] => US [patent_app_date] => 2013-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5974 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14069188 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/069188
Memory device selecting different column selection lines based on different offset values and memory system including the same Oct 30, 2013 Issued
Array ( [id] => 11200851 [patent_doc_number] => 09431068 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-30 [patent_title] => 'Dynamic random access memory (DRAM) with low variation transistor peripheral circuits' [patent_app_type] => utility [patent_app_number] => 14/068756 [patent_app_country] => US [patent_app_date] => 2013-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 32 [patent_no_of_words] => 17604 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14068756 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/068756
Dynamic random access memory (DRAM) with low variation transistor peripheral circuits Oct 30, 2013 Issued
Array ( [id] => 9447939 [patent_doc_number] => 20140119108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'MEMORY SYSTEM INCLUDING NONVOLATILE MEMORY AND METHOD OF OPERATING NONVOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 14/068076 [patent_app_country] => US [patent_app_date] => 2013-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10266 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14068076 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/068076
Method of operating a nonvolatile memory by reprogramming failed cells using a reinforced program pulse in an idle state and memory system thereof Oct 30, 2013 Issued
Array ( [id] => 9475788 [patent_doc_number] => 20140133251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'SEMICONDUCTOR STORAGE APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/069056 [patent_app_country] => US [patent_app_date] => 2013-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 14233 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14069056 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/069056
Semiconductor storage apparatus with a data-to-be-written output circuit for carrying out an early data write Oct 30, 2013 Issued
Array ( [id] => 9447927 [patent_doc_number] => 20140119096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'SEMICONDUCTOR MEMORY APPARATUS, PROGRAM METHOD AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 14/068382 [patent_app_country] => US [patent_app_date] => 2013-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 9285 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14068382 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/068382
Resistive semiconductor memory capable of performing incremental step pulse programming (ISPP) based on digital code values of memory cells Oct 30, 2013 Issued
Array ( [id] => 9475778 [patent_doc_number] => 20140133241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-15 [patent_title] => 'Memory Controllers and User Systems Including the Same' [patent_app_type] => utility [patent_app_number] => 14/068746 [patent_app_country] => US [patent_app_date] => 2013-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5077 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14068746 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/068746
Memory controller equipped with a compensation circuit for supplying an additional power to a memory device and user system including the same Oct 30, 2013 Issued
Array ( [id] => 11214528 [patent_doc_number] => 09443566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Identification of a condition of a sector of memory cells in a non-volatile memory' [patent_app_type] => utility [patent_app_number] => 14/061977 [patent_app_country] => US [patent_app_date] => 2013-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6689 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14061977 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/061977
Identification of a condition of a sector of memory cells in a non-volatile memory Oct 23, 2013 Issued
Array ( [id] => 10402441 [patent_doc_number] => 20150287450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-08 [patent_title] => 'THERMALLY ASSISTED MRAM CELL AND METHOD FOR WRITING A PLURALITY OF BITS IN THE MRAM CELL' [patent_app_type] => utility [patent_app_number] => 14/438365 [patent_app_country] => US [patent_app_date] => 2013-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4360 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14438365 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/438365
Thermally assisted multi-level MRAM cell and method for writing a plurality of bits in the MRAM cell Oct 10, 2013 Issued
Array ( [id] => 13030547 [patent_doc_number] => 10037896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-31 [patent_title] => Electro-assisted transfer and fabrication of wire arrays [patent_app_type] => utility [patent_app_number] => 14/907253 [patent_app_country] => US [patent_app_date] => 2013-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 7033 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14907253 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/907253
Electro-assisted transfer and fabrication of wire arrays Sep 25, 2013 Issued
Array ( [id] => 9718599 [patent_doc_number] => 20140254297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-11 [patent_title] => 'METHOD AND APPARATUS FOR MEMORY REPAIR' [patent_app_type] => utility [patent_app_number] => 14/036997 [patent_app_country] => US [patent_app_date] => 2013-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3697 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14036997 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/036997
Memory integrated circuit with a page register/status memory capable of storing only a subset of row blocks of main column blocks Sep 24, 2013 Issued
Array ( [id] => 9403215 [patent_doc_number] => 08693275 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-08 [patent_title] => 'Method and apparatus for calibrating a read/write channel in a memory arrangement' [patent_app_type] => utility [patent_app_number] => 14/021712 [patent_app_country] => US [patent_app_date] => 2013-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3493 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14021712 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/021712
Method and apparatus for calibrating a read/write channel in a memory arrangement Sep 8, 2013 Issued
Array ( [id] => 9261198 [patent_doc_number] => 20130343127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-26 [patent_title] => 'METHOD FOR MEMORY CELL ERASURE WITH A PROGRAMMING MONITOR OF REFERENCE CELLS' [patent_app_type] => utility [patent_app_number] => 13/971075 [patent_app_country] => US [patent_app_date] => 2013-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14654 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13971075 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/971075
Method and devices for memory cell erasure with a programming monitor of reference cells Aug 19, 2013 Issued
Array ( [id] => 9190163 [patent_doc_number] => 20130329478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-12 [patent_title] => 'Semiconductor Devices Having a Three Dimensional Stacked Structure and Methods of De-Skewing Data Therein' [patent_app_type] => utility [patent_app_number] => 13/937367 [patent_app_country] => US [patent_app_date] => 2013-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 15660 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13937367 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/937367
Three-dimensional semiconductor memory device having compensating data skewing according to interlayer timing delay and method of de-skewing data therein Jul 8, 2013 Issued
Array ( [id] => 10833092 [patent_doc_number] => 08861272 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-10-14 [patent_title] => 'System and method for data recovery in a solid state storage device using optimal reference voltage values of a related storage element' [patent_app_type] => utility [patent_app_number] => 13/935221 [patent_app_country] => US [patent_app_date] => 2013-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3618 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13935221 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/935221
System and method for data recovery in a solid state storage device using optimal reference voltage values of a related storage element Jul 2, 2013 Issued
Array ( [id] => 9106102 [patent_doc_number] => 20130279234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-24 [patent_title] => 'ANTIFUSE UNIT CELL OF NONVOLATILE MEMORY DEVICE FOR ENHANCING DATA SENSE MARGIN AND NONVOLATILE MEMORY DEVICE WITH THE SAME' [patent_app_type] => utility [patent_app_number] => 13/921521 [patent_app_country] => US [patent_app_date] => 2013-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7888 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13921521 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/921521
Antifuse unit cell of nonvolatile memory device for enhancing data sense margin and nonvolatile memory device with the same Jun 18, 2013 Issued
Array ( [id] => 9377307 [patent_doc_number] => 08681577 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-25 [patent_title] => 'Semiconductor memory integrated device having a precharge circuit with thin-film transistors gated by a voltage higher than a power supply voltage' [patent_app_type] => utility [patent_app_number] => 13/918425 [patent_app_country] => US [patent_app_date] => 2013-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 9084 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13918425 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/918425
Semiconductor memory integrated device having a precharge circuit with thin-film transistors gated by a voltage higher than a power supply voltage Jun 13, 2013 Issued
Array ( [id] => 9052981 [patent_doc_number] => 20130250695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'METHOD FOR ERASING MEMORY CELLS IN A FLASH MEMORY DEVICE USING A POSITIVE WELL BIAS VOLTAGE AND A NEGATIVE WORD LINE VOLTAGE' [patent_app_type] => utility [patent_app_number] => 13/895591 [patent_app_country] => US [patent_app_date] => 2013-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4306 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13895591 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/895591
Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage May 15, 2013 Issued
Array ( [id] => 9442483 [patent_doc_number] => 08711605 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Resistive memory element sensing using averaging' [patent_app_type] => utility [patent_app_number] => 13/868544 [patent_app_country] => US [patent_app_date] => 2013-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3727 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13868544 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/868544
Resistive memory element sensing using averaging Apr 22, 2013 Issued
Array ( [id] => 9712651 [patent_doc_number] => 08837236 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Hybrid nonvolatile shadowed DRAM with an overlapping region between a volatile storage die and a nonvolatile storage die' [patent_app_type] => utility [patent_app_number] => 13/867963 [patent_app_country] => US [patent_app_date] => 2013-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 6326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13867963 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/867963
Hybrid nonvolatile shadowed DRAM with an overlapping region between a volatile storage die and a nonvolatile storage die Apr 21, 2013 Issued
Array ( [id] => 9014915 [patent_doc_number] => 20130229879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-05 [patent_title] => 'METHOD OF USING MULTIPLEXING CIRCUIT FOR HIGH SPEED, LOW LEAKAGE, COLUMN-MULTIPLEXING MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 13/866782 [patent_app_country] => US [patent_app_date] => 2013-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2817 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13866782 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/866782
Method of using multiplexing circuit for high speed, low leakage, column-multiplexing memory devices Apr 18, 2013 Issued
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