Search

Andrew Q. Tran

Examiner (ID: 7081)

Most Active Art Unit
2824
Art Unit(s)
2511, 2812, 2818, 2824, 2825, 2827
Total Applications
1878
Issued Applications
1746
Pending Applications
27
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9014915 [patent_doc_number] => 20130229879 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-05 [patent_title] => 'METHOD OF USING MULTIPLEXING CIRCUIT FOR HIGH SPEED, LOW LEAKAGE, COLUMN-MULTIPLEXING MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 13/866782 [patent_app_country] => US [patent_app_date] => 2013-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2817 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13866782 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/866782
Method of using multiplexing circuit for high speed, low leakage, column-multiplexing memory devices Apr 18, 2013 Issued
Array ( [id] => 9784327 [patent_doc_number] => 20140301147 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-09 [patent_title] => 'SEMICONDUCTOR STORAGE WITH A FLOATING DETECTION CIRCUITRY AND FLOATING DETECTION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/857680 [patent_app_country] => US [patent_app_date] => 2013-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4285 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13857680 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/857680
Semiconductor storage with a floating detection circuitry and floating detection method thereof Apr 4, 2013 Issued
Array ( [id] => 9764116 [patent_doc_number] => 08848452 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-09-30 [patent_title] => 'Erase verification circuitry for simultaneously and consecutively verifying a plurality of odd and even-numbered flash memory transistors and method thereof' [patent_app_type] => utility [patent_app_number] => 13/856816 [patent_app_country] => US [patent_app_date] => 2013-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5100 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13856816 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/856816
Erase verification circuitry for simultaneously and consecutively verifying a plurality of odd and even-numbered flash memory transistors and method thereof Apr 3, 2013 Issued
Array ( [id] => 9080293 [patent_doc_number] => 20130265823 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-10 [patent_title] => 'Nonvolatile Semiconductor Memory Device Cross-Reference to Related Applications' [patent_app_type] => utility [patent_app_number] => 13/855902 [patent_app_country] => US [patent_app_date] => 2013-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4771 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13855902 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/855902
Read disturb control in a nonvolatile semiconductor memory device having P-type memory cell transistor Apr 2, 2013 Issued
Array ( [id] => 13650857 [patent_doc_number] => 09851742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-12-26 [patent_title] => Photonic quantum memory with time-bin entangled photon storage [patent_app_type] => utility [patent_app_number] => 13/856218 [patent_app_country] => US [patent_app_date] => 2013-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6405 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13856218 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/856218
Photonic quantum memory with time-bin entangled photon storage Apr 2, 2013 Issued
Array ( [id] => 13292941 [patent_doc_number] => 10157669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Method of storing and retrieving information for a resistive random access memory (RRAM) with multi-memory cells per bit [patent_app_type] => utility [patent_app_number] => 13/855208 [patent_app_country] => US [patent_app_date] => 2013-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3420 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13855208 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/855208
Method of storing and retrieving information for a resistive random access memory (RRAM) with multi-memory cells per bit Apr 1, 2013 Issued
Array ( [id] => 9733366 [patent_doc_number] => 20140269076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-09-18 [patent_title] => 'NON-VOLATILE MEMORY AND PROGRAMMING IN THEREOF' [patent_app_type] => utility [patent_app_number] => 13/855490 [patent_app_country] => US [patent_app_date] => 2013-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4477 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13855490 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/855490
Non-volatile memory capable of programming cells by hot carrier injection based on a threshold voltage of a control cell Apr 1, 2013 Issued
Array ( [id] => 9770055 [patent_doc_number] => 20140293718 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'MEMORY CONTROLLER AND METHOD OF CALIBRATING A MEMORY CONTROLLER' [patent_app_type] => utility [patent_app_number] => 13/854226 [patent_app_country] => US [patent_app_date] => 2013-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8320 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13854226 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/854226
Memory controller and method of calibrating a memory controller Mar 31, 2013 Issued
Array ( [id] => 9770020 [patent_doc_number] => 20140293683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'MAGNETO-RESISTIVE EFFECT ELEMENT' [patent_app_type] => utility [patent_app_number] => 13/854336 [patent_app_country] => US [patent_app_date] => 2013-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6587 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13854336 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/854336
MAGNETO-RESISTIVE EFFECT ELEMENT Mar 31, 2013 Pending
Array ( [id] => 10556819 [patent_doc_number] => 09281021 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'Method and apparatus for reduced read latency for consecutive read operations of memory of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 13/854548 [patent_app_country] => US [patent_app_date] => 2013-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2749 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13854548 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/854548
Method and apparatus for reduced read latency for consecutive read operations of memory of an integrated circuit Mar 31, 2013 Issued
Array ( [id] => 9650430 [patent_doc_number] => 08804456 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-08-12 [patent_title] => 'Delay locked loop (DLL) system for a memory device with wide operating frequency via a variable supply applied to a delay line' [patent_app_type] => utility [patent_app_number] => 13/853032 [patent_app_country] => US [patent_app_date] => 2013-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2281 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13853032 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/853032
Delay locked loop (DLL) system for a memory device with wide operating frequency via a variable supply applied to a delay line Mar 27, 2013 Issued
Array ( [id] => 10696640 [patent_doc_number] => 20160042787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'APPARATUS AND METHOD FOR STORAGE DEVICE READING' [patent_app_type] => utility [patent_app_number] => 14/760191 [patent_app_country] => US [patent_app_date] => 2013-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3624 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14760191 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/760191
Apparatus and method for reading a storage device with a ring oscillator and a time-to-digital circuit Mar 27, 2013 Issued
Array ( [id] => 10899837 [patent_doc_number] => 08923066 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-12-30 [patent_title] => 'Storage of read thresholds for NAND flash storage using linear approximation' [patent_app_type] => utility [patent_app_number] => 13/852934 [patent_app_country] => US [patent_app_date] => 2013-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6810 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13852934 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/852934
Storage of read thresholds for NAND flash storage using linear approximation Mar 27, 2013 Issued
Array ( [id] => 9770041 [patent_doc_number] => 20140293704 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'Auto-Suspend and Auto-Resume Operations for a Multi-Die NAND Memory Device' [patent_app_type] => utility [patent_app_number] => 13/852992 [patent_app_country] => US [patent_app_date] => 2013-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5733 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13852992 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/852992
Auto-suspend and auto-resume operations for a multi-die NAND memory device to reduce peak power consumption Mar 27, 2013 Issued
Array ( [id] => 8988379 [patent_doc_number] => 20130215660 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'VARIABLE RESISTANCE MEMORY DEVICE HAVING EQUAL RESISTANCES BETWEEN SIGNAL PATHS REGARDLESS OF LOCATION OF MEMORY CELLS WITHIN THE MEMORY ARRAY' [patent_app_type] => utility [patent_app_number] => 13/844905 [patent_app_country] => US [patent_app_date] => 2013-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5662 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13844905 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/844905
VARIABLE RESISTANCE MEMORY DEVICE HAVING EQUAL RESISTANCES BETWEEN SIGNAL PATHS REGARDLESS OF LOCATION OF MEMORY CELLS WITHIN THE MEMORY ARRAY Mar 15, 2013 Abandoned
Array ( [id] => 8988384 [patent_doc_number] => 20130215665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'VARIABLE RESISTANCE MEMORY DEVICE HAVING EQUAL RESISTANCES BETWEEN SIGNAL PATHS REGARDLESS OF LOCATION OF MEMORY CELLS WITHIN THE MEMORY ARRAY' [patent_app_type] => utility [patent_app_number] => 13/844899 [patent_app_country] => US [patent_app_date] => 2013-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5664 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13844899 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/844899
Variable resistance memory device having equal resistances between signal paths regardless of location of memory cells within the memory array Mar 15, 2013 Issued
Array ( [id] => 11811336 [patent_doc_number] => 09715909 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-25 [patent_title] => 'Apparatuses and methods for controlling data timing in a multi-memory system' [patent_app_type] => utility [patent_app_number] => 13/804461 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8007 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13804461 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/804461
Apparatuses and methods for controlling data timing in a multi-memory system Mar 13, 2013 Issued
Array ( [id] => 10047211 [patent_doc_number] => 09087611 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'System and method for integrated circuit memory repair with binary-encoded repair control word' [patent_app_type] => utility [patent_app_number] => 13/804421 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4406 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13804421 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/804421
System and method for integrated circuit memory repair with binary-encoded repair control word Mar 13, 2013 Issued
Array ( [id] => 8962176 [patent_doc_number] => 20130201778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-08 [patent_title] => 'SEMICONDUCTOR DEVICE CAPABLE OF ADJUSTING MEMORY PAGE SIZE BASED ON A ROW ADDRESS AND A BANK ADDRESS' [patent_app_type] => utility [patent_app_number] => 13/828604 [patent_app_country] => US [patent_app_date] => 2013-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7879 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13828604 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/828604
Semiconductor device capable of adjusting memory page size based on a row address, a bank address and a power supply voltage Mar 13, 2013 Issued
Array ( [id] => 9945866 [patent_doc_number] => 08995182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-31 [patent_title] => 'Coarse and fine programming in a solid state memory' [patent_app_type] => utility [patent_app_number] => 13/796602 [patent_app_country] => US [patent_app_date] => 2013-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 9097 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13796602 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/796602
Coarse and fine programming in a solid state memory Mar 11, 2013 Issued
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