Search

Andrew Q. Tran

Examiner (ID: 7081)

Most Active Art Unit
2824
Art Unit(s)
2511, 2812, 2818, 2824, 2825, 2827
Total Applications
1878
Issued Applications
1746
Pending Applications
27
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8962149 [patent_doc_number] => 20130201752 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-08 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/790351 [patent_app_country] => US [patent_app_date] => 2013-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 28564 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13790351 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/790351
Non-volatile semiconductor memory device equipped with an oxide semiconductor writing transistor having a small off-state current Mar 7, 2013 Issued
Array ( [id] => 8988413 [patent_doc_number] => 20130215694 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-22 [patent_title] => 'Method for semiconductor memory interface device with noise cancellation circuitry having phase and gain adjustments' [patent_app_type] => utility [patent_app_number] => 13/790306 [patent_app_country] => US [patent_app_date] => 2013-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6388 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13790306 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/790306
Method for semiconductor memory interface device with noise cancellation circuitry having phase and gain adjustments Mar 7, 2013 Issued
Array ( [id] => 10138280 [patent_doc_number] => 09171601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-10-27 [patent_title] => 'Scalable magnetic memory cell with reduced write current' [patent_app_type] => utility [patent_app_number] => 13/762799 [patent_app_country] => US [patent_app_date] => 2013-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 6962 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13762799 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/762799
Scalable magnetic memory cell with reduced write current Feb 7, 2013 Issued
Array ( [id] => 11194128 [patent_doc_number] => 09424946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-08-23 [patent_title] => 'Non-volatile buffering to enable sloppy writes and fast write verification' [patent_app_type] => utility [patent_app_number] => 13/762806 [patent_app_country] => US [patent_app_date] => 2013-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 8444 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13762806 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/762806
Non-volatile buffering to enable sloppy writes and fast write verification Feb 7, 2013 Issued
Array ( [id] => 9221628 [patent_doc_number] => 20140016403 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-16 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/762940 [patent_app_country] => US [patent_app_date] => 2013-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 10486 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13762940 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/762940
Hierarchical wordline loadless 4GST-SRAM with a small cell area Feb 7, 2013 Issued
Array ( [id] => 9553882 [patent_doc_number] => 08760942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'Resistive memory device capable of blocking a current flowing through a memory cell for fast quenching' [patent_app_type] => utility [patent_app_number] => 13/762428 [patent_app_country] => US [patent_app_date] => 2013-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5488 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13762428 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/762428
Resistive memory device capable of blocking a current flowing through a memory cell for fast quenching Feb 7, 2013 Issued
Array ( [id] => 9819339 [patent_doc_number] => 08929134 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-06 [patent_title] => 'Method of programming a flash memory by enhancing the channel voltage of a program-inhibit bit line with a boosted inhibit scheme' [patent_app_type] => utility [patent_app_number] => 13/762896 [patent_app_country] => US [patent_app_date] => 2013-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3879 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13762896 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/762896
Method of programming a flash memory by enhancing the channel voltage of a program-inhibit bit line with a boosted inhibit scheme Feb 7, 2013 Issued
Array ( [id] => 9119825 [patent_doc_number] => 20130286747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-31 [patent_title] => 'NONVOLATILE MEMORY DEVICE AND RELATED METHOD OF OPERATION' [patent_app_type] => utility [patent_app_number] => 13/761196 [patent_app_country] => US [patent_app_date] => 2013-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 13086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13761196 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/761196
Method of programming a 3-dimensional nonvolatile memory device based on a program order of a selected page and a location of a string selection line Feb 6, 2013 Issued
Array ( [id] => 9628104 [patent_doc_number] => 08797793 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'Self-referenced MRAM element with linear sensing signal' [patent_app_type] => utility [patent_app_number] => 13/761292 [patent_app_country] => US [patent_app_date] => 2013-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3661 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13761292 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/761292
Self-referenced MRAM element with linear sensing signal Feb 6, 2013 Issued
Array ( [id] => 9640898 [patent_doc_number] => 20140219009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'LOW VOLTAGE BOOTSTRAPPING METHOD FOR WRITE ASSIST' [patent_app_type] => utility [patent_app_number] => 13/761646 [patent_app_country] => US [patent_app_date] => 2013-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7244 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13761646 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/761646
Write driver circuit with low voltage bootstrapping for write assist Feb 6, 2013 Issued
Array ( [id] => 9991202 [patent_doc_number] => 09036417 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-19 [patent_title] => 'On chip dynamic read level scan and error detection for nonvolatile storage' [patent_app_type] => utility [patent_app_number] => 13/761956 [patent_app_country] => US [patent_app_date] => 2013-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 36 [patent_no_of_words] => 17069 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13761956 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/761956
On chip dynamic read level scan and error detection for nonvolatile storage Feb 6, 2013 Issued
Array ( [id] => 9640895 [patent_doc_number] => 20140219007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-07 [patent_title] => 'DRAM WITH SEGMENTED PAGE CONFIGURATION' [patent_app_type] => utility [patent_app_number] => 13/761996 [patent_app_country] => US [patent_app_date] => 2013-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2725 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13761996 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/761996
DRAM WITH SEGMENTED PAGE CONFIGURATION Feb 6, 2013 Abandoned
Array ( [id] => 10590387 [patent_doc_number] => 09312007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Memory device and method having charge level assignments selected to minimize signal coupling' [patent_app_type] => utility [patent_app_number] => 13/759716 [patent_app_country] => US [patent_app_date] => 2013-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6379 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13759716 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/759716
Memory device and method having charge level assignments selected to minimize signal coupling Feb 4, 2013 Issued
Array ( [id] => 9021913 [patent_doc_number] => 08531903 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-09-10 [patent_title] => 'Method and apparatus for calibrating a read/write channel in a memory arrangement' [patent_app_type] => utility [patent_app_number] => 13/752121 [patent_app_country] => US [patent_app_date] => 2013-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3465 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13752121 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/752121
Method and apparatus for calibrating a read/write channel in a memory arrangement Jan 27, 2013 Issued
Array ( [id] => 8882583 [patent_doc_number] => 20130155767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'APPARATUSES AND METHODS FOR SENSING A PHASE-CHANGE TEST CELL AND DETERMINING CHANGES TO THE TEST CELL RESISTANCE DUE TO THERMAL EXPOSURE' [patent_app_type] => utility [patent_app_number] => 13/735791 [patent_app_country] => US [patent_app_date] => 2013-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2761 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13735791 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/735791
Sensing phase-change memory/test cells for determining whether a cell resistance has changed due to thermal exposure Jan 6, 2013 Issued
Array ( [id] => 8790676 [patent_doc_number] => 20130107645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'Nonvolatile Memory And Writing Method Thereof, And Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 13/687013 [patent_app_country] => US [patent_app_date] => 2012-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17427 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13687013 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/687013
Nonvolatile Memory And Writing Method Thereof, And Semiconductor Device Nov 27, 2012 Abandoned
Array ( [id] => 9415228 [patent_doc_number] => 08699274 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-15 [patent_title] => 'Flash memory device and operating method for concurrently applying different bias voltages to dummy memory cells and regular memory cells during erasure' [patent_app_type] => utility [patent_app_number] => 13/680812 [patent_app_country] => US [patent_app_date] => 2012-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 5900 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13680812 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/680812
Flash memory device and operating method for concurrently applying different bias voltages to dummy memory cells and regular memory cells during erasure Nov 18, 2012 Issued
Array ( [id] => 9114641 [patent_doc_number] => 08570826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'Memory device having data paths facilitating array/contact consolidation and/or swapping' [patent_app_type] => utility [patent_app_number] => 13/672018 [patent_app_country] => US [patent_app_date] => 2012-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6330 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13672018 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/672018
Memory device having data paths facilitating array/contact consolidation and/or swapping Nov 7, 2012 Issued
Array ( [id] => 9939119 [patent_doc_number] => 08988937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-24 [patent_title] => 'Pre-charge during programming for 3D memory using gate-induced drain leakage' [patent_app_type] => utility [patent_app_number] => 13/659418 [patent_app_country] => US [patent_app_date] => 2012-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 12566 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13659418 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/659418
Pre-charge during programming for 3D memory using gate-induced drain leakage Oct 23, 2012 Issued
Array ( [id] => 8670002 [patent_doc_number] => 20130044540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'PROGRAMMING AT LEAST ONE MULTI-LEVEL PHASE CHANGE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 13/659364 [patent_app_country] => US [patent_app_date] => 2012-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5437 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13659364 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/659364
Apparatus and method for programming a multi-level phase change memory (PCM) cell based on an actual resistance value and a reference resistance value Oct 23, 2012 Issued
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