Search

Andrew Q. Tran

Examiner (ID: 7081)

Most Active Art Unit
2824
Art Unit(s)
2511, 2812, 2818, 2824, 2825, 2827
Total Applications
1878
Issued Applications
1746
Pending Applications
27
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9434182 [patent_doc_number] => 20140112088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'CONTROL CIRCUIT, MEMORY DEVICE AND VOLTAGE CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/658834 [patent_app_country] => US [patent_app_date] => 2012-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2827 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13658834 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/658834
Semiconductor memory device for controlling an internal supply voltage based on a clock frequency of an external clock signal and a look-up table Oct 23, 2012 Issued
Array ( [id] => 11411507 [patent_doc_number] => 09558817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-31 [patent_title] => 'Conditioning phase change memory cells' [patent_app_type] => utility [patent_app_number] => 13/659038 [patent_app_country] => US [patent_app_date] => 2012-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 28 [patent_no_of_words] => 7037 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13659038 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/659038
Conditioning phase change memory cells Oct 23, 2012 Issued
Array ( [id] => 8790656 [patent_doc_number] => 20130107625 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-02 [patent_title] => 'Flash Memory Apparatus and Method for Controlling Flash Memory Apparatus' [patent_app_type] => utility [patent_app_number] => 13/658086 [patent_app_country] => US [patent_app_date] => 2012-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3534 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13658086 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/658086
Flash memory apparatus capable of extending data retention and improving data reliability, and method for controlling the same Oct 22, 2012 Issued
Array ( [id] => 9434157 [patent_doc_number] => 20140112063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'IMPLEMENTING SDRAM HAVING NO RAS TO CAS DELAY IN WRITE OPERATION' [patent_app_type] => utility [patent_app_number] => 13/658226 [patent_app_country] => US [patent_app_date] => 2012-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3080 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13658226 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/658226
Implementing SDRAM having no RAS to CAS delay in write operation Oct 22, 2012 Issued
Array ( [id] => 10099686 [patent_doc_number] => 09136001 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Signal-to-Noise Ratio (SNR) estimation in analog memory cells based on optimal read thresholds' [patent_app_type] => utility [patent_app_number] => 13/657150 [patent_app_country] => US [patent_app_date] => 2012-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 6752 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13657150 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/657150
Signal-to-Noise Ratio (SNR) estimation in analog memory cells based on optimal read thresholds Oct 21, 2012 Issued
Array ( [id] => 8669998 [patent_doc_number] => 20130044536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-21 [patent_title] => 'ARRAY-BASED INTEGRATED CIRCUIT WITH REDUCED PROXIMITY EFFECTS' [patent_app_type] => utility [patent_app_number] => 13/655512 [patent_app_country] => US [patent_app_date] => 2012-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9127 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13655512 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/655512
Array-based integrated circuit with reduced proximity effects Oct 18, 2012 Issued
Array ( [id] => 9420310 [patent_doc_number] => 20140104960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'Methods and Apparatus for Designing and Constructing High-Speed Memory Circuits' [patent_app_type] => utility [patent_app_number] => 13/651698 [patent_app_country] => US [patent_app_date] => 2012-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6446 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13651698 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/651698
Methods and Apparatus for Designing and Constructing High-Speed Memory Circuits Oct 14, 2012 Abandoned
Array ( [id] => 9771459 [patent_doc_number] => 20140295122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-02 [patent_title] => 'METHOD FOR WAFER-LEVEL MANUFACTURING OF OBJECTS AND CORRESPONDING SEMI-FINISHED PRODUCTS' [patent_app_type] => utility [patent_app_number] => 14/346804 [patent_app_country] => US [patent_app_date] => 2012-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6510 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14346804 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/346804
Method for wafer-level manufacturing of objects and corresponding semi-finished products Sep 30, 2012 Issued
Array ( [id] => 11585630 [patent_doc_number] => 09640279 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-05-02 [patent_title] => 'Apparatus and method for built-in test and repair of 3D-IC memory' [patent_app_type] => utility [patent_app_number] => 13/611109 [patent_app_country] => US [patent_app_date] => 2012-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5265 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13611109 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/611109
Apparatus and method for built-in test and repair of 3D-IC memory Sep 11, 2012 Issued
Array ( [id] => 9337204 [patent_doc_number] => 20140063986 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-06 [patent_title] => 'SRAM LOCAL EVALUATION AND WRITE LOGIC FOR COLUMN SELECTION' [patent_app_type] => utility [patent_app_number] => 13/604800 [patent_app_country] => US [patent_app_date] => 2012-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4486 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604800 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604800
SRAM local evaluation and write logic for column selection Sep 5, 2012 Issued
Array ( [id] => 9313368 [patent_doc_number] => 08654595 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-18 [patent_title] => 'Nonvolatile memory device with a clamping voltage generation circuit for compensating the variations in memory cell parameters' [patent_app_type] => utility [patent_app_number] => 13/604688 [patent_app_country] => US [patent_app_date] => 2012-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 10560 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604688 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604688
Nonvolatile memory device with a clamping voltage generation circuit for compensating the variations in memory cell parameters Sep 5, 2012 Issued
Array ( [id] => 9819355 [patent_doc_number] => 08929150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-06 [patent_title] => 'Nonvolatile memory apparatus capable of determining an application time of a program voltage applied to a selected word line' [patent_app_type] => utility [patent_app_number] => 13/604442 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3385 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604442 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604442
Nonvolatile memory apparatus capable of determining an application time of a program voltage applied to a selected word line Sep 4, 2012 Issued
Array ( [id] => 8975115 [patent_doc_number] => 20130208545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'SEMICONDUCTOR MEMORY APPARATUS, PROGRAM METHOD THEREOF, AND DATA PROCESSING SYSTEM USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/604116 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604116 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604116
SEMICONDUCTOR MEMORY APPARATUS, PROGRAM METHOD THEREOF, AND DATA PROCESSING SYSTEM USING THE SAME Sep 4, 2012 Abandoned
Array ( [id] => 9133471 [patent_doc_number] => 20130294185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-07 [patent_title] => 'SENSE AMPLIFIER CIRCUIT AND SEMICONDUCTOR DEVICE USING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/604472 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4943 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604472 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604472
Semiconductor device with a sense amplifier unit responsive to a voltage change of input signals and a sense control signal Sep 4, 2012 Issued
Array ( [id] => 10195532 [patent_doc_number] => 09224445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-29 [patent_title] => 'Semiconductor memory apparatus with main memory blocks and redundant memory blocks sharing a common global data line' [patent_app_type] => utility [patent_app_number] => 13/604240 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8577 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604240 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604240
Semiconductor memory apparatus with main memory blocks and redundant memory blocks sharing a common global data line Sep 4, 2012 Issued
Array ( [id] => 8696136 [patent_doc_number] => 20130058145 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-07 [patent_title] => 'MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/604308 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 21246 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604308 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604308
Semiconductor memory device capable of screening a weak bit and repairing the same Sep 4, 2012 Issued
Array ( [id] => 9313369 [patent_doc_number] => 08654596 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-18 [patent_title] => 'Nonvolatile semiconductor storage device equipped with a comparison buffer for reducing power consumption during write' [patent_app_type] => utility [patent_app_number] => 13/604338 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10633 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604338 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604338
Nonvolatile semiconductor storage device equipped with a comparison buffer for reducing power consumption during write Sep 4, 2012 Issued
Array ( [id] => 9484791 [patent_doc_number] => 08730748 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-20 [patent_title] => 'Semiconductor memory apparatus equipped with an error control circuit for preventing coupling noise' [patent_app_type] => utility [patent_app_number] => 13/604504 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4886 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604504 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604504
Semiconductor memory apparatus equipped with an error control circuit for preventing coupling noise Sep 4, 2012 Issued
Array ( [id] => 9228564 [patent_doc_number] => 08634238 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-21 [patent_title] => 'Magnetic memory element having an adjustment layer for reducing a leakage magnetic field from a reference layer and magnetic memory thereof' [patent_app_type] => utility [patent_app_number] => 13/604386 [patent_app_country] => US [patent_app_date] => 2012-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4425 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13604386 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/604386
Magnetic memory element having an adjustment layer for reducing a leakage magnetic field from a reference layer and magnetic memory thereof Sep 4, 2012 Issued
Array ( [id] => 8565141 [patent_doc_number] => 20120327712 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'METHOD FOR MEMORY CELL ERASURE WITH A PROGRAMMING MONITOR OF REFERENCE CELLS' [patent_app_type] => utility [patent_app_number] => 13/602762 [patent_app_country] => US [patent_app_date] => 2012-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14637 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13602762 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/602762
Method for memory cell erasure with a programming monitor of reference cells Sep 3, 2012 Issued
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