
Andrew Q. Tran
Examiner (ID: 7081)
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2511, 2812, 2818, 2824, 2825, 2827 |
| Total Applications | 1878 |
| Issued Applications | 1746 |
| Pending Applications | 27 |
| Abandoned Applications | 106 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
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[id] => 8565161
[patent_doc_number] => 20120327732
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[patent_issue_date] => 2012-12-27
[patent_title] => 'SEMICONDUCTOR INTEGRATED DEVICE'
[patent_app_type] => utility
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Array
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[patent_issue_date] => 2014-02-04
[patent_title] => 'Hierarchical memory arbitration technique for disparate sources'
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Array
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Array
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[patent_title] => 'Optimal channel design for memory devices for providing a high-speed memory interface'
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Array
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[patent_title] => 'COARSE AND FINE PROGRAMMING IN A SOLID STATE MEMORY'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/589844 | Configurable multi-port memory device and method thereof | Aug 19, 2012 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/572815 | Method of increasing a timing margin for relaying data to a memory array | Aug 12, 2012 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/567134 | BTI-Independent Source Biasing of Memory Arrays | Aug 5, 2012 | Abandoned |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/566180 | Determining whether a memory cell state is in a valley between adjacent data states | Aug 2, 2012 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/564878 | Multi-valued logic device having nonvolatile memory device | Aug 1, 2012 | Issued |
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/565666 | Semiconductor device having plural circuit blocks operating at the same timing | Aug 1, 2012 | Issued |
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