Search

Andrew Q. Tran

Examiner (ID: 7081)

Most Active Art Unit
2824
Art Unit(s)
2511, 2812, 2818, 2824, 2825, 2827
Total Applications
1878
Issued Applications
1746
Pending Applications
27
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8565161 [patent_doc_number] => 20120327732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'SEMICONDUCTOR INTEGRATED DEVICE' [patent_app_type] => utility [patent_app_number] => 13/600412 [patent_app_country] => US [patent_app_date] => 2012-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9087 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13600412 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/600412
Semiconductor memory integrated device having a precharge circuit with thin-film transistors gated by a voltage higher than a power supply voltage Aug 30, 2012 Issued
Array ( [id] => 9289283 [patent_doc_number] => 08645639 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-04 [patent_title] => 'Hierarchical memory arbitration technique for disparate sources' [patent_app_type] => utility [patent_app_number] => 13/600614 [patent_app_country] => US [patent_app_date] => 2012-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13600614 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/600614
Hierarchical memory arbitration technique for disparate sources Aug 30, 2012 Issued
Array ( [id] => 9274678 [patent_doc_number] => 08638620 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-28 [patent_title] => 'Random access memory for use in an emulation environment' [patent_app_type] => utility [patent_app_number] => 13/599682 [patent_app_country] => US [patent_app_date] => 2012-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 3874 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13599682 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/599682
Random access memory for use in an emulation environment Aug 29, 2012 Issued
Array ( [id] => 9356883 [patent_doc_number] => 08675429 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-03-18 [patent_title] => 'Optimal channel design for memory devices for providing a high-speed memory interface' [patent_app_type] => utility [patent_app_number] => 13/597895 [patent_app_country] => US [patent_app_date] => 2012-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 4280 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13597895 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/597895
Optimal channel design for memory devices for providing a high-speed memory interface Aug 28, 2012 Issued
Array ( [id] => 9256053 [patent_doc_number] => 08619481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-31 [patent_title] => 'Switched interface stacked-die memory architecture' [patent_app_type] => utility [patent_app_number] => 13/595294 [patent_app_country] => US [patent_app_date] => 2012-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7533 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13595294 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/595294
Switched interface stacked-die memory architecture Aug 26, 2012 Issued
Array ( [id] => 8515095 [patent_doc_number] => 20120314503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'COARSE AND FINE PROGRAMMING IN A SOLID STATE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/590376 [patent_app_country] => US [patent_app_date] => 2012-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8980 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13590376 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/590376
Coarse and fine programming in a solid state memory Aug 20, 2012 Issued
Array ( [id] => 8515115 [patent_doc_number] => 20120314523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'MULTI-PORT MEMORY DEVICES AND METHODS' [patent_app_type] => utility [patent_app_number] => 13/589844 [patent_app_country] => US [patent_app_date] => 2012-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3239 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13589844 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/589844
Configurable multi-port memory device and method thereof Aug 19, 2012 Issued
Array ( [id] => 8508162 [patent_doc_number] => 20120307570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'METHOD FOR RELAYING DATA TO MEMORY ARRAY' [patent_app_type] => utility [patent_app_number] => 13/572815 [patent_app_country] => US [patent_app_date] => 2012-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5865 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13572815 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/572815
Method of increasing a timing margin for relaying data to a memory array Aug 12, 2012 Issued
Array ( [id] => 9128670 [patent_doc_number] => 08576626 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-05 [patent_title] => 'Flash memory system capable of operating in a random access mode' [patent_app_type] => utility [patent_app_number] => 13/570960 [patent_app_country] => US [patent_app_date] => 2012-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3950 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13570960 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/570960
Flash memory system capable of operating in a random access mode Aug 8, 2012 Issued
Array ( [id] => 9292978 [patent_doc_number] => 20140036612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'BTI-Independent Source Biasing of Memory Arrays' [patent_app_type] => utility [patent_app_number] => 13/567134 [patent_app_country] => US [patent_app_date] => 2012-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2506 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13567134 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/567134
BTI-Independent Source Biasing of Memory Arrays Aug 5, 2012 Abandoned
Array ( [id] => 9292955 [patent_doc_number] => 20140036589 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'MEMORY CELL STATE IN A VALLEY BETWEEN ADJACENT DATA STATES' [patent_app_type] => utility [patent_app_number] => 13/566180 [patent_app_country] => US [patent_app_date] => 2012-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7657 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13566180 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/566180
Determining whether a memory cell state is in a valley between adjacent data states Aug 2, 2012 Issued
Array ( [id] => 10158352 [patent_doc_number] => 09190135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-17 [patent_title] => 'Organic ferroelectric material based random access memory' [patent_app_type] => utility [patent_app_number] => 13/566830 [patent_app_country] => US [patent_app_date] => 2012-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3742 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13566830 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/566830
Organic ferroelectric material based random access memory Aug 2, 2012 Issued
Array ( [id] => 9141914 [patent_doc_number] => 08582388 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-11-12 [patent_title] => 'Serial advanced technology attachment dual in-line memory module (SATA DIMM) capable of preventing data loss' [patent_app_type] => utility [patent_app_number] => 13/564762 [patent_app_country] => US [patent_app_date] => 2012-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 955 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13564762 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/564762
Serial advanced technology attachment dual in-line memory module (SATA DIMM) capable of preventing data loss Aug 1, 2012 Issued
Array ( [id] => 8820015 [patent_doc_number] => 20130121059 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-05-16 [patent_title] => 'MULTI-VALUED LOGIC DEVICE HAVING NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/564878 [patent_app_country] => US [patent_app_date] => 2012-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15602 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13564878 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/564878
Multi-valued logic device having nonvolatile memory device Aug 1, 2012 Issued
Array ( [id] => 8648186 [patent_doc_number] => 20130033916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-07 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING PLURAL CIRCUIT BLOCKS THAT OPERATE THE SAME TIMING' [patent_app_type] => utility [patent_app_number] => 13/565666 [patent_app_country] => US [patent_app_date] => 2012-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 43 [patent_figures_cnt] => 43 [patent_no_of_words] => 15814 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13565666 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/565666
Semiconductor device having plural circuit blocks operating at the same timing Aug 1, 2012 Issued
Array ( [id] => 9292947 [patent_doc_number] => 20140036581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-06 [patent_title] => 'SENSE AMPLIFIER FOR STATIC RANDOM ACCESS MEMORY' [patent_app_type] => utility [patent_app_number] => 13/563960 [patent_app_country] => US [patent_app_date] => 2012-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5017 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13563960 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/563960
Sense amplifier for static random access memory with a pair of complementary data lines isolated from a corresponding pair of complementary bit lines Jul 31, 2012 Issued
Array ( [id] => 9101142 [patent_doc_number] => 08565031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Method for reading phase change memory cells having a clamping circuit' [patent_app_type] => utility [patent_app_number] => 13/561172 [patent_app_country] => US [patent_app_date] => 2012-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7849 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13561172 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/561172
Method for reading phase change memory cells having a clamping circuit Jul 29, 2012 Issued
Array ( [id] => 10531060 [patent_doc_number] => 09257200 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-02-09 [patent_title] => 'Bit error testing and training in double data rate (DDR) memory system' [patent_app_type] => utility [patent_app_number] => 13/559741 [patent_app_country] => US [patent_app_date] => 2012-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 5402 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13559741 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/559741
Bit error testing and training in double data rate (DDR) memory system Jul 26, 2012 Issued
Array ( [id] => 9429224 [patent_doc_number] => 08705306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-22 [patent_title] => 'Method for using a bit specific reference level to read a phase change memory' [patent_app_type] => utility [patent_app_number] => 13/555346 [patent_app_country] => US [patent_app_date] => 2012-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 6788 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13555346 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/555346
Method for using a bit specific reference level to read a phase change memory Jul 22, 2012 Issued
Array ( [id] => 8482046 [patent_doc_number] => 20120281453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-08 [patent_title] => 'VARIABLE RESISTANCE NONVOLATILE STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 13/534315 [patent_app_country] => US [patent_app_date] => 2012-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 21700 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13534315 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/534315
Variable resistance nonvolatile storage device with oxygen-deficient oxide layer and asymmetric substrate bias effect Jun 26, 2012 Issued
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