Andrew Q. Tran

Array ( [id] => 16448487 [patent_doc_number] => 10840418 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-17 [patent_title] => Fabricating parabolic-shaped LEDs [patent_app_type] => utility [patent_app_number] => 16/424325 [patent_app_country] => US [patent_app_date] => 2019-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 21805 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16424325 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16417943 [patent_doc_number] => 10825844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-03 [patent_title] => Thin film transistor array substrate minimizing unwanted reflection of external light and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 16/424388 [patent_app_country] => US [patent_app_date] => 2019-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 10263 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16424388 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17181417 [patent_doc_number] => 11158666 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-26 [patent_title] => Multiple wavelength light-emitting diode epitaxial structure with asymmetric multiple quantum wells [patent_app_type] => utility [patent_app_number] => 16/423573 [patent_app_country] => US [patent_app_date] => 2019-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4592 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16423573 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16448477 [patent_doc_number] => 10840408 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-11-17 [patent_title] => Enhanced efficiency of LED structure with n-doped quantum barriers [patent_app_type] => utility [patent_app_number] => 16/423407 [patent_app_country] => US [patent_app_date] => 2019-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4614 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16423407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16324186 [patent_doc_number] => 10784158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-22 [patent_title] => Area-selective deposition of a tantalum silicide TaSi [patent_app_type] => utility [patent_app_number] => 16/412923 [patent_app_country] => US [patent_app_date] => 2019-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 6089 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16412923 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14676081 [patent_doc_number] => 20190237155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => MEMORY INTEGRATED CIRCUIT WITH A PAGE REGISTER/STATUS MEMORY CAPABLE OF STORING ONLY A SUBSET OF ROW BLOCKS OF MAIN COLUMN BLOCKS [patent_app_type] => utility [patent_app_number] => 16/381391 [patent_app_country] => US [patent_app_date] => 2019-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3706 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16381391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16272340 [patent_doc_number] => 20200273828 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/281092 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281092 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16270133 [patent_doc_number] => 20200271620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-27 [patent_title] => ION-SENSITIVE FIELD EFFECT TRANSISTOR (ISFET) WITH ENHANCED SENSITIVITY [patent_app_type] => utility [patent_app_number] => 16/281183 [patent_app_country] => US [patent_app_date] => 2019-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8401 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16281183 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16210495 [patent_doc_number] => 20200243485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => Semiconductor device package having integrated circuits with I/O interface circuits powered by the same core voltage [patent_app_type] => utility [patent_app_number] => 16/262869 [patent_app_country] => US [patent_app_date] => 2019-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2067 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16262869 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14558541 [patent_doc_number] => 10347743 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Vertical transport fin field effect transistor (VT FinFET) having an uniform L-shaped inner spacer [patent_app_type] => utility [patent_app_number] => 16/239212 [patent_app_country] => US [patent_app_date] => 2019-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5253 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16239212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14205535 [patent_doc_number] => 10269894 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-23 [patent_title] => Method of manufacturing a deep trench capacitor with a filled trench and a doped region serving as a capacitor electrode [patent_app_type] => utility [patent_app_number] => 16/229735 [patent_app_country] => US [patent_app_date] => 2018-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 5797 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16229735 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14397609 [patent_doc_number] => 10312095 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-06-04 [patent_title] => Recessed solid state apparatuses [patent_app_type] => utility [patent_app_number] => 16/163602 [patent_app_country] => US [patent_app_date] => 2018-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2975 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16163602 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15703621 [patent_doc_number] => 10607998 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-31 [patent_title] => Integrated circuitry, DRAM circuitry, method of forming a plurality of conductive vias, and method of forming DRAM circuitry [patent_app_type] => utility [patent_app_number] => 16/148148 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 5869 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16148148 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15717931 [patent_doc_number] => 20200105733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => SEMICONDUCTOR DEVICE HAVING VOLTAGE REGULATORS EMBEDDED IN LAYERED PACKAGE [patent_app_type] => utility [patent_app_number] => 16/146801 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6113 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16146801 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14267689 [patent_doc_number] => 10283415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Semiconductor structure with a bump having a width larger than a width of fin shaped structures and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 16/132460 [patent_app_country] => US [patent_app_date] => 2018-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3678 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16132460 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16163377 [patent_doc_number] => 20200219921 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => IMAGING ELEMENT AND IMAGING DEVICE [patent_app_type] => utility [patent_app_number] => 16/349745 [patent_app_country] => US [patent_app_date] => 2018-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13961 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16349745 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15760625 [patent_doc_number] => 10622444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => FinFET semiconductor device with a dummy gate, first gate spacer and second gate spacer [patent_app_type] => utility [patent_app_number] => 16/124521 [patent_app_country] => US [patent_app_date] => 2018-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 60 [patent_figures_cnt] => 60 [patent_no_of_words] => 12547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16124521 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13785733 [patent_doc_number] => 20190006405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-03 [patent_title] => IMAGE PICKUP APPARATUS, ENDOSCOPE AND IMAGE PICKUP APPARATUS MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 16/122974 [patent_app_country] => US [patent_app_date] => 2018-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4430 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16122974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13832825 [patent_doc_number] => 20190019897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-17 [patent_title] => FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/119415 [patent_app_country] => US [patent_app_date] => 2018-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5939 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16119415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14267771 [patent_doc_number] => 10283457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Method for lithographically forming wafer identification marks and alignment marks [patent_app_type] => utility [patent_app_number] => 16/114567 [patent_app_country] => US [patent_app_date] => 2018-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16114567 [rel_patent_id] =>[rel_patent_doc_number] =>)