Search

Andrew Q. Tran

Examiner (ID: 7081)

Most Active Art Unit
2824
Art Unit(s)
2511, 2812, 2818, 2824, 2825, 2827
Total Applications
1878
Issued Applications
1746
Pending Applications
27
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8263661 [patent_doc_number] => 20120163095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/332682 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6009 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13332682 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/332682
SEMICONDUCTOR MEMORY DEVICE Dec 20, 2011 Abandoned
Array ( [id] => 8890152 [patent_doc_number] => 20130163336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-27 [patent_title] => 'Erase Operation With Controlled Select Gate Voltage For 3D Non-Volatile Memory' [patent_app_type] => utility [patent_app_number] => 13/332844 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 13532 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13332844 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/332844
Erase operation with controlled select gate voltage for 3D non-volatile memory Dec 20, 2011 Issued
Array ( [id] => 9525758 [patent_doc_number] => 08750042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-10 [patent_title] => 'Combined simultaneous sensing of multiple wordlines in a post-write read (PWR) and detection of NAND failures' [patent_app_type] => utility [patent_app_number] => 13/332780 [patent_app_country] => US [patent_app_date] => 2011-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 52 [patent_no_of_words] => 31034 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13332780 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/332780
Combined simultaneous sensing of multiple wordlines in a post-write read (PWR) and detection of NAND failures Dec 20, 2011 Issued
Array ( [id] => 9313363 [patent_doc_number] => 08654590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-18 [patent_title] => 'Nonvolatile memory device performing a program verification with sense signals based on program data of adjacent memory cells and program method thereof' [patent_app_type] => utility [patent_app_number] => 13/331820 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5859 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13331820 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/331820
Nonvolatile memory device performing a program verification with sense signals based on program data of adjacent memory cells and program method thereof Dec 19, 2011 Issued
Array ( [id] => 8346058 [patent_doc_number] => 20120206981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-16 [patent_title] => 'METHOD AND DEVICE FOR WRITING DATA' [patent_app_type] => utility [patent_app_number] => 13/331817 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2498 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13331817 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/331817
Method and device for writing block data to an embedded DRAM free of address conflicts Dec 19, 2011 Issued
Array ( [id] => 9300979 [patent_doc_number] => 08649214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-11 [patent_title] => 'Magnetic memory including magnetic memory cells integrated with a magnetic shift register and methods thereof' [patent_app_type] => utility [patent_app_number] => 13/332230 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 7747 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13332230 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/332230
Magnetic memory including magnetic memory cells integrated with a magnetic shift register and methods thereof Dec 19, 2011 Issued
Array ( [id] => 8871875 [patent_doc_number] => 08467257 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-18 [patent_title] => 'Circuit and method for generating a sense amplifier enable signal based on a voltage level of a tracking bitline' [patent_app_type] => utility [patent_app_number] => 13/332045 [patent_app_country] => US [patent_app_date] => 2011-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3701 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13332045 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/332045
Circuit and method for generating a sense amplifier enable signal based on a voltage level of a tracking bitline Dec 19, 2011 Issued
Array ( [id] => 8318527 [patent_doc_number] => 08233311 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Variable resistance nonvolatile storage device having a source line formed of parallel wiring layers connected to each other through vias' [patent_app_type] => utility [patent_app_number] => 13/310894 [patent_app_country] => US [patent_app_date] => 2011-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 21711 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13310894 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/310894
Variable resistance nonvolatile storage device having a source line formed of parallel wiring layers connected to each other through vias Dec 4, 2011 Issued
Array ( [id] => 8258817 [patent_doc_number] => 08208319 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-26 [patent_title] => 'Method for indicating a non-flash nonvolatile multiple-type three-dimensional memory' [patent_app_type] => utility [patent_app_number] => 13/303002 [patent_app_country] => US [patent_app_date] => 2011-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 8761 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13303002 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/303002
Method for indicating a non-flash nonvolatile multiple-type three-dimensional memory Nov 21, 2011 Issued
Array ( [id] => 8665973 [patent_doc_number] => 08379442 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-19 [patent_title] => 'Memory device and method having charge level assignments selected to minimize signal coupling' [patent_app_type] => utility [patent_app_number] => 13/292783 [patent_app_country] => US [patent_app_date] => 2011-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6344 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13292783 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/292783
Memory device and method having charge level assignments selected to minimize signal coupling Nov 8, 2011 Issued
Array ( [id] => 7789559 [patent_doc_number] => 20120051115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-01 [patent_title] => 'RESISTANCE CHANGING MEMORY CELL ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 13/289553 [patent_app_country] => US [patent_app_date] => 2011-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 11984 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20120051115.pdf [firstpage_image] =>[orig_patent_app_number] => 13289553 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/289553
Resistive changing memory cell architecture having a select transistor coupled to a resistance changing memory element Nov 3, 2011 Issued
Array ( [id] => 8318526 [patent_doc_number] => 08233313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-31 [patent_title] => 'Conductive organic non-volatile memory device with nanocrystals embedded in an amorphous barrier layer' [patent_app_type] => utility [patent_app_number] => 13/286861 [patent_app_country] => US [patent_app_date] => 2011-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 68 [patent_no_of_words] => 13683 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13286861 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/286861
Conductive organic non-volatile memory device with nanocrystals embedded in an amorphous barrier layer Oct 31, 2011 Issued
Array ( [id] => 11486601 [patent_doc_number] => 09592664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-14 [patent_title] => 'Circuit that selects EPROMs individually and in parallel' [patent_app_type] => utility [patent_app_number] => 14/343133 [patent_app_country] => US [patent_app_date] => 2011-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 9196 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14343133 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/343133
Circuit that selects EPROMs individually and in parallel Sep 26, 2011 Issued
Array ( [id] => 7706409 [patent_doc_number] => 20120001175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'SEMICONDUCTOR DEVICE CAPABLE OF SUPPRESSING A COUPLING EFFECT OF A TEST-DISABLE TRANSMISSION LINE' [patent_app_type] => utility [patent_app_number] => 13/229086 [patent_app_country] => US [patent_app_date] => 2011-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2884 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13229086 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/229086
Semiconductor device capable of suppressing a coupling effect of a test-disable transmission line Sep 8, 2011 Issued
Array ( [id] => 8167409 [patent_doc_number] => 08174882 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-08 [patent_title] => 'Method of programming a non-volatile memory device for enhancing a channel boosting of a bit line inhibited from programming' [patent_app_type] => utility [patent_app_number] => 13/226148 [patent_app_country] => US [patent_app_date] => 2011-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3575 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/174/08174882.pdf [firstpage_image] =>[orig_patent_app_number] => 13226148 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/226148
Method of programming a non-volatile memory device for enhancing a channel boosting of a bit line inhibited from programming Sep 5, 2011 Issued
Array ( [id] => 7585577 [patent_doc_number] => 20110280087 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'CIRCUIT FOR SUPPLYING A REFERENCE VOLTAGE IN A SEMICONDUCTOR MEMORY DEVICE FOR TESTING AN INTERNAL VOLTAGE GENERATOR THEREIN' [patent_app_type] => utility [patent_app_number] => 13/190103 [patent_app_country] => US [patent_app_date] => 2011-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3675 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20110280087.pdf [firstpage_image] =>[orig_patent_app_number] => 13190103 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/190103
Circuit for supplying a reference voltage in a semiconductor memory device for testing an internal voltage generator therein Jul 24, 2011 Issued
Array ( [id] => 7560097 [patent_doc_number] => 20110273929 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'SEMICONDUCTOR MAGNETIC MEMORY INTEGRATING A MAGNETIC TUNNELING JUNCTION ABOVE A FLOATING-GATE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 13/186796 [patent_app_country] => US [patent_app_date] => 2011-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5383 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20110273929.pdf [firstpage_image] =>[orig_patent_app_number] => 13186796 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/186796
Method for programming a semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell Jul 19, 2011 Issued
Array ( [id] => 8471283 [patent_doc_number] => 08300472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Low noise sense amplifier array and method for nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 13/178690 [patent_app_country] => US [patent_app_date] => 2011-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 12336 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13178690 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/178690
Low noise sense amplifier array and method for nonvolatile memory Jul 7, 2011 Issued
Array ( [id] => 8835915 [patent_doc_number] => 08451680 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-28 [patent_title] => 'Method of driving a semiconductor memory device with a sense amplifier controller for maintaining the connection of a previously selected memory cell array' [patent_app_type] => utility [patent_app_number] => 13/166476 [patent_app_country] => US [patent_app_date] => 2011-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5032 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13166476 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/166476
Method of driving a semiconductor memory device with a sense amplifier controller for maintaining the connection of a previously selected memory cell array Jun 21, 2011 Issued
Array ( [id] => 9114642 [patent_doc_number] => 08570827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'Physical organization of memory to reduce power consumption' [patent_app_type] => utility [patent_app_number] => 13/164306 [patent_app_country] => US [patent_app_date] => 2011-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7697 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13164306 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/164306
Physical organization of memory to reduce power consumption Jun 19, 2011 Issued
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