Search

Andrew Q. Tran

Examiner (ID: 7081)

Most Active Art Unit
2824
Art Unit(s)
2511, 2812, 2818, 2824, 2825, 2827
Total Applications
1878
Issued Applications
1746
Pending Applications
27
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8494687 [patent_doc_number] => 20120294095 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-22 [patent_title] => 'Dynamic Level Shifter' [patent_app_type] => utility [patent_app_number] => 13/108730 [patent_app_country] => US [patent_app_date] => 2011-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3853 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13108730 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/108730
Dynamic level shifter for interfacing signals referenced to different power supply domains May 15, 2011 Issued
Array ( [id] => 8544914 [patent_doc_number] => 08320211 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-11-27 [patent_title] => 'Current-sense amplifier with low-offset adjustment and method of low-offset adjustment thereof' [patent_app_type] => utility [patent_app_number] => 13/108550 [patent_app_country] => US [patent_app_date] => 2011-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3410 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13108550 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/108550
Current-sense amplifier with low-offset adjustment and method of low-offset adjustment thereof May 15, 2011 Issued
Array ( [id] => 8238939 [patent_doc_number] => 20120147676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-14 [patent_title] => 'NON-VOLATILE STORAGE SYSTEM WITH SHARED BIT LINES CONNECTED TO SINGLE SELECTION DEVICE' [patent_app_type] => utility [patent_app_number] => 13/107686 [patent_app_country] => US [patent_app_date] => 2011-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 10549 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13107686 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/107686
Non-volatile storage system with shared bit lines connected to a single selection device May 12, 2011 Issued
Array ( [id] => 8068209 [patent_doc_number] => 20110242920 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'VOLTAGE SENSING CIRCUIT CAPABLE OF CONTROLLING A PUMP VOLTAGE STABLY GENERATED IN A LOW VOLTAGE ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 13/101558 [patent_app_country] => US [patent_app_date] => 2011-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4970 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20110242920.pdf [firstpage_image] =>[orig_patent_app_number] => 13101558 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/101558
Voltage sensing circuit capable of controlling a pump voltage stably generated in a low voltage environment May 4, 2011 Issued
Array ( [id] => 5933498 [patent_doc_number] => 20110210794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-01 [patent_title] => 'VOLTAGE SENSING CIRCUIT CAPABLE OF CONTROLLING A PUMP VOLTAGE STABLY GENERATED IN A LOW VOLTAGE ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 13/101411 [patent_app_country] => US [patent_app_date] => 2011-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4972 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20110210794.pdf [firstpage_image] =>[orig_patent_app_number] => 13101411 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/101411
Voltage sensing circuit capable of controlling a pump voltage stably generated in a low voltage environment May 4, 2011 Issued
Array ( [id] => 8154804 [patent_doc_number] => 08169831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-01 [patent_title] => 'High speed sense amplifier array and method for non-volatile memory' [patent_app_type] => utility [patent_app_number] => 13/100164 [patent_app_country] => US [patent_app_date] => 2011-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 13987 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/169/08169831.pdf [firstpage_image] =>[orig_patent_app_number] => 13100164 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/100164
High speed sense amplifier array and method for non-volatile memory May 2, 2011 Issued
Array ( [id] => 8631417 [patent_doc_number] => 08363501 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-01-29 [patent_title] => 'Method and apparatus for calibrating a read/write channel in a memory arrangement' [patent_app_type] => utility [patent_app_number] => 13/099997 [patent_app_country] => US [patent_app_date] => 2011-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3416 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13099997 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/099997
Method and apparatus for calibrating a read/write channel in a memory arrangement May 2, 2011 Issued
Array ( [id] => 8376690 [patent_doc_number] => 08259491 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-04 [patent_title] => 'Coarse and fine programming in a solid state memory' [patent_app_type] => utility [patent_app_number] => 13/094409 [patent_app_country] => US [patent_app_date] => 2011-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 8966 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13094409 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/094409
Coarse and fine programming in a solid state memory Apr 25, 2011 Issued
Array ( [id] => 6108560 [patent_doc_number] => 20110188312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-04 [patent_title] => 'METHOD FOR MEMORY CELL ERASURE WITH A PROGRAMMING MONITOR OF REFERENCE CELLS' [patent_app_type] => utility [patent_app_number] => 13/082965 [patent_app_country] => US [patent_app_date] => 2011-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 14598 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20110188312.pdf [firstpage_image] =>[orig_patent_app_number] => 13082965 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/082965
Method for memory cell erasure with a programming monitor of reference cells Apr 7, 2011 Issued
Array ( [id] => 8761760 [patent_doc_number] => 08422290 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Methods of reading data in a NAND flash memory device with a fringe voltage applied to a conductive layer' [patent_app_type] => utility [patent_app_number] => 13/072022 [patent_app_country] => US [patent_app_date] => 2011-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6759 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13072022 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/072022
Methods of reading data in a NAND flash memory device with a fringe voltage applied to a conductive layer Mar 24, 2011 Issued
Array ( [id] => 8898016 [patent_doc_number] => 08477543 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-02 [patent_title] => 'Data input circuit with a valid strobe signal generation circuit' [patent_app_type] => utility [patent_app_number] => 13/051060 [patent_app_country] => US [patent_app_date] => 2011-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4625 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13051060 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/051060
Data input circuit with a valid strobe signal generation circuit Mar 17, 2011 Issued
Array ( [id] => 8068281 [patent_doc_number] => 20110242881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-06 [patent_title] => 'SRAM DEVICE' [patent_app_type] => utility [patent_app_number] => 13/051022 [patent_app_country] => US [patent_app_date] => 2011-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3777 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0242/20110242881.pdf [firstpage_image] =>[orig_patent_app_number] => 13051022 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/051022
SRAM device capable of independently controlling a double-gate selection transistor for maintaining an optimal read margin and read speed Mar 17, 2011 Issued
Array ( [id] => 7485048 [patent_doc_number] => 20110235396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 13/051110 [patent_app_country] => US [patent_app_date] => 2011-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3799 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20110235396.pdf [firstpage_image] =>[orig_patent_app_number] => 13051110 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/051110
Resistance semiconductor memory device having a bit line supplied with a compensating current based on a leak current detected during a forming operation Mar 17, 2011 Issued
Array ( [id] => 8544863 [patent_doc_number] => 08320160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'NAND architecture having a resistive memory cell connected to a control gate of a field-effect transistor' [patent_app_type] => utility [patent_app_number] => 13/051296 [patent_app_country] => US [patent_app_date] => 2011-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 9005 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13051296 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/051296
NAND architecture having a resistive memory cell connected to a control gate of a field-effect transistor Mar 17, 2011 Issued
Array ( [id] => 8407893 [patent_doc_number] => 20120239961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'SYNCHRONOUS DATA PROCESSING SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/050932 [patent_app_country] => US [patent_app_date] => 2011-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3329 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13050932 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/050932
Synchronous data processing system for reliable transfer of data irrespective of propagation delays and process, voltage and temperature (PVT) variations Mar 17, 2011 Issued
Array ( [id] => 8539380 [patent_doc_number] => 08315103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Flash memory device and operating method for concurrently applying different bias voltages to dummy memory cells and regular memory cells during erasure' [patent_app_type] => utility [patent_app_number] => 13/047178 [patent_app_country] => US [patent_app_date] => 2011-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 5866 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13047178 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/047178
Flash memory device and operating method for concurrently applying different bias voltages to dummy memory cells and regular memory cells during erasure Mar 13, 2011 Issued
Array ( [id] => 8544916 [patent_doc_number] => 08320213 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Memory device having data paths' [patent_app_type] => utility [patent_app_number] => 13/042204 [patent_app_country] => US [patent_app_date] => 2011-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6299 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13042204 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/042204
Memory device having data paths Mar 6, 2011 Issued
Array ( [id] => 9577069 [patent_doc_number] => 08767496 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-01 [patent_title] => 'Bias sensing in DRAM sense amplifiers through voltage-coupling/decoupling device' [patent_app_type] => utility [patent_app_number] => 13/039169 [patent_app_country] => US [patent_app_date] => 2011-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7448 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13039169 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/039169
Bias sensing in DRAM sense amplifiers through voltage-coupling/decoupling device Mar 1, 2011 Issued
Array ( [id] => 5966914 [patent_doc_number] => 20110149669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'Sense Amplifier and Data Sensing Method Thereof' [patent_app_type] => utility [patent_app_number] => 13/038606 [patent_app_country] => US [patent_app_date] => 2011-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3968 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20110149669.pdf [firstpage_image] =>[orig_patent_app_number] => 13038606 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/038606
Sense amplifier with a sensing transmission transistor and a reference transmission transistor operating in saturation regions and data sensing method thereof Mar 1, 2011 Issued
Array ( [id] => 6086641 [patent_doc_number] => 20110216612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-08 [patent_title] => 'Device' [patent_app_type] => utility [patent_app_number] => 12/929965 [patent_app_country] => US [patent_app_date] => 2011-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7484 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20110216612.pdf [firstpage_image] =>[orig_patent_app_number] => 12929965 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/929965
Semiconductor device capable of minimizing mutual effects between two different operations therein Feb 27, 2011 Issued
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