Search

Andrew Q. Tran

Examiner (ID: 7081)

Most Active Art Unit
2824
Art Unit(s)
2511, 2812, 2818, 2824, 2825, 2827
Total Applications
1878
Issued Applications
1746
Pending Applications
27
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8216748 [patent_doc_number] => 08194494 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Word line block/select circuit with repair address decision unit' [patent_app_type] => utility [patent_app_number] => 13/036398 [patent_app_country] => US [patent_app_date] => 2011-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1998 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/194/08194494.pdf [firstpage_image] =>[orig_patent_app_number] => 13036398 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/036398
Word line block/select circuit with repair address decision unit Feb 27, 2011 Issued
Array ( [id] => 5999285 [patent_doc_number] => 20110116315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-19 [patent_title] => 'Nonvolatile Semiconductor Memory Device' [patent_app_type] => utility [patent_app_number] => 13/012030 [patent_app_country] => US [patent_app_date] => 2011-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 19054 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20110116315.pdf [firstpage_image] =>[orig_patent_app_number] => 13012030 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/012030
Nonvolatile semiconductor memory device with a voltage setting circuit for a step-up shift test Jan 23, 2011 Issued
Array ( [id] => 8459431 [patent_doc_number] => 08295108 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-23 [patent_title] => 'Architecture, system and method for compressing repair data in an integrated circuit (IC) design' [patent_app_type] => utility [patent_app_number] => 13/011696 [patent_app_country] => US [patent_app_date] => 2011-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 5516 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13011696 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/011696
Architecture, system and method for compressing repair data in an integrated circuit (IC) design Jan 20, 2011 Issued
Array ( [id] => 9240713 [patent_doc_number] => 08605510 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-10 [patent_title] => 'Flash memory device and method of verifying the same including a compensated erase verify voltage' [patent_app_type] => utility [patent_app_number] => 13/009499 [patent_app_country] => US [patent_app_date] => 2011-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3434 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13009499 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/009499
Flash memory device and method of verifying the same including a compensated erase verify voltage Jan 18, 2011 Issued
Array ( [id] => 8376700 [patent_doc_number] => 08259501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-04 [patent_title] => 'Flash memory system operating in a random access mode' [patent_app_type] => utility [patent_app_number] => 13/006068 [patent_app_country] => US [patent_app_date] => 2011-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3922 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13006068 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/006068
Flash memory system operating in a random access mode Jan 12, 2011 Issued
Array ( [id] => 6172769 [patent_doc_number] => 20110176348 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/987279 [patent_app_country] => US [patent_app_date] => 2011-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 28516 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20110176348.pdf [firstpage_image] =>[orig_patent_app_number] => 12987279 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/987279
Non-volatile semiconductor memory device equipped with an oxide semiconductor writing transistor having a small off-state current Jan 9, 2011 Issued
Array ( [id] => 8216686 [patent_doc_number] => 08194461 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-05 [patent_title] => 'Semiconductor memory device having dummy cells in NAND strings applied with an additional program voltage after erasure and prior to data programming' [patent_app_type] => utility [patent_app_number] => 12/985427 [patent_app_country] => US [patent_app_date] => 2011-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 30 [patent_no_of_words] => 8492 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/194/08194461.pdf [firstpage_image] =>[orig_patent_app_number] => 12985427 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/985427
Semiconductor memory device having dummy cells in NAND strings applied with an additional program voltage after erasure and prior to data programming Jan 5, 2011 Issued
Array ( [id] => 5983209 [patent_doc_number] => 20110096582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-28 [patent_title] => 'CONTENT ADDRESSABLE MEMORY WITH CONCURRENT TWO-DIMENSIONAL SEARCH CAPABILITY IN BOTH ROW AND COLUMN DIRECTIONS' [patent_app_type] => utility [patent_app_number] => 12/983995 [patent_app_country] => US [patent_app_date] => 2011-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4966 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20110096582.pdf [firstpage_image] =>[orig_patent_app_number] => 12983995 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/983995
Content addressable memory with concurrent read and search/compare operations at the same memory cell Jan 3, 2011 Issued
Array ( [id] => 8644173 [patent_doc_number] => 08369167 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-02-05 [patent_title] => 'Semiconductor memory device and method of testing a sense amplifier of the same' [patent_app_type] => utility [patent_app_number] => 12/984217 [patent_app_country] => US [patent_app_date] => 2011-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7841 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12984217 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/984217
Semiconductor memory device and method of testing a sense amplifier of the same Jan 3, 2011 Issued
Array ( [id] => 6157387 [patent_doc_number] => 20110158002 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/981927 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3663 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0158/20110158002.pdf [firstpage_image] =>[orig_patent_app_number] => 12981927 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/981927
Semiconductor memory device and method of precharging the same with a first and second precharge voltage simultaneously applied to a bit line Dec 29, 2010 Issued
Array ( [id] => 10899828 [patent_doc_number] => 08923057 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-30 [patent_title] => 'Three-dimensional semiconductor memory device with active patterns and electrodes arranged above a substrate' [patent_app_type] => utility [patent_app_number] => 12/981625 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 10525 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12981625 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/981625
Three-dimensional semiconductor memory device with active patterns and electrodes arranged above a substrate Dec 29, 2010 Issued
Array ( [id] => 8136771 [patent_doc_number] => 20120092935 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/982825 [patent_app_country] => US [patent_app_date] => 2010-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3836 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20120092935.pdf [firstpage_image] =>[orig_patent_app_number] => 12982825 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/982825
Semiconductor memory device integrating flash memory and resistive/magnetic memory Dec 29, 2010 Issued
Array ( [id] => 6037686 [patent_doc_number] => 20110090735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'EXPANDED PROGRAMMING WINDOW FOR NON-VOLATILE MULTILEVEL MEMORY CELLS' [patent_app_type] => utility [patent_app_number] => 12/971587 [patent_app_country] => US [patent_app_date] => 2010-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0090/20110090735.pdf [firstpage_image] =>[orig_patent_app_number] => 12971587 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/971587
Expanded programming window for non-volatile multilevel memory cells Dec 16, 2010 Issued
Array ( [id] => 9553892 [patent_doc_number] => 08760952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-24 [patent_title] => 'Overlapping interconnect signal lines for reducing capacitive coupling effects' [patent_app_type] => utility [patent_app_number] => 12/971273 [patent_app_country] => US [patent_app_date] => 2010-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8933 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12971273 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/971273
Overlapping interconnect signal lines for reducing capacitive coupling effects Dec 16, 2010 Issued
Array ( [id] => 8702719 [patent_doc_number] => 08395946 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Data access apparatus and associated method for accessing data using internally generated clocks' [patent_app_type] => utility [patent_app_number] => 12/968719 [patent_app_country] => US [patent_app_date] => 2010-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4636 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12968719 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/968719
Data access apparatus and associated method for accessing data using internally generated clocks Dec 14, 2010 Issued
Array ( [id] => 6026961 [patent_doc_number] => 20110079858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-07 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE HAVING A SENSE AMPLIFIER CIRCUIT WITH DECREASED OFFSET' [patent_app_type] => utility [patent_app_number] => 12/967728 [patent_app_country] => US [patent_app_date] => 2010-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11916 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20110079858.pdf [firstpage_image] =>[orig_patent_app_number] => 12967728 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/967728
Semiconductor memory device having a sense amplifier circuit with decreased offset Dec 13, 2010 Issued
Array ( [id] => 4611910 [patent_doc_number] => 07995402 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Method for erasing a semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell' [patent_app_type] => utility [patent_app_number] => 12/966430 [patent_app_country] => US [patent_app_date] => 2010-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 17 [patent_no_of_words] => 5378 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/995/07995402.pdf [firstpage_image] =>[orig_patent_app_number] => 12966430 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/966430
Method for erasing a semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell Dec 12, 2010 Issued
Array ( [id] => 6181018 [patent_doc_number] => 20110122693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 12/962343 [patent_app_country] => US [patent_app_date] => 2010-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10256 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20110122693.pdf [firstpage_image] =>[orig_patent_app_number] => 12962343 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/962343
Flash memory array system including a top gate memory cell Dec 6, 2010 Issued
Array ( [id] => 8219430 [patent_doc_number] => 20120134202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-31 [patent_title] => 'VERIFY OR READ PULSE FOR PHASE CHANGE MEMORY AND SWITCH' [patent_app_type] => utility [patent_app_number] => 12/956853 [patent_app_country] => US [patent_app_date] => 2010-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7135 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12956853 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/956853
Verify or read pulse for phase change memory and switch Nov 29, 2010 Issued
Array ( [id] => 6140498 [patent_doc_number] => 20110128781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'SEMICONDUCTOR MEMORY CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/954723 [patent_app_country] => US [patent_app_date] => 2010-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12409 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20110128781.pdf [firstpage_image] =>[orig_patent_app_number] => 12954723 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/954723
Semiconductor memory circuit equipped with multiplexer for reducing coupling capacitance of non-selected main bit lines Nov 25, 2010 Issued
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