Andrew Q. Tran

Array ( [id] => 8207652 [patent_doc_number] => 20120127772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'LOW POWER SRAM BASED CONTENT ADDRESSABLE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/953759 [patent_app_country] => US [patent_app_date] => 2010-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2857 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20120127772.pdf [firstpage_image] =>[orig_patent_app_number] => 12953759 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4559941 [patent_doc_number] => 07961529 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-14 [patent_title] => 'Processor including vertically stacked third-dimensional embedded re-writeable non-volatile memory and registers' [patent_app_type] => utility [patent_app_number] => 12/927795 [patent_app_country] => US [patent_app_date] => 2010-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3682 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/961/07961529.pdf [firstpage_image] =>[orig_patent_app_number] => 12927795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9324911 [patent_doc_number] => 08659941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-25 [patent_title] => 'Semiconductor memory cell having an oxide semiconductor transistor and erasable by ultraviolet light' [patent_app_type] => utility [patent_app_number] => 12/951899 [patent_app_country] => US [patent_app_date] => 2010-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 68 [patent_no_of_words] => 20802 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12951899 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8702728 [patent_doc_number] => 08395955 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'Semiconductor memory interface device with a noise cancellation circuit having a phase and gain adjustment circuitry' [patent_app_type] => utility [patent_app_number] => 12/948193 [patent_app_country] => US [patent_app_date] => 2010-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6373 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12948193 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8761763 [patent_doc_number] => 08422293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Self-powered event detection device' [patent_app_type] => utility [patent_app_number] => 12/945138 [patent_app_country] => US [patent_app_date] => 2010-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 9612 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12945138 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8726945 [patent_doc_number] => 08406080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-26 [patent_title] => 'Data output control circuit of a double data rate (DDR) synchronous semiconductor memory device responsive to a delay locked loop (DLL) clock and method thereof' [patent_app_type] => utility [patent_app_number] => 12/940727 [patent_app_country] => US [patent_app_date] => 2010-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 5277 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12940727 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8169405 [patent_doc_number] => 20120106225 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'Array-Based Integrated Circuit with Reduced Proximity Effects' [patent_app_type] => utility [patent_app_number] => 12/913479 [patent_app_country] => US [patent_app_date] => 2010-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9103 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20120106225.pdf [firstpage_image] =>[orig_patent_app_number] => 12913479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7520044 [patent_doc_number] => 07974149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'Thin-film memory system equipped with a thin-film address decoder and memory controller' [patent_app_type] => utility [patent_app_number] => 12/909113 [patent_app_country] => US [patent_app_date] => 2010-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 34 [patent_no_of_words] => 17581 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/974/07974149.pdf [firstpage_image] =>[orig_patent_app_number] => 12909113 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8835906 [patent_doc_number] => 08451671 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-28 [patent_title] => 'Multiplexing circuit for high-speed, low leakage, column-multiplexing memory devices' [patent_app_type] => utility [patent_app_number] => 12/905317 [patent_app_country] => US [patent_app_date] => 2010-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2808 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12905317 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8847740 [patent_doc_number] => 08456930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Variable resistance memory device having equal resistances between signal paths regardless of location of memory cells within the memory array' [patent_app_type] => utility [patent_app_number] => 12/899985 [patent_app_country] => US [patent_app_date] => 2010-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5657 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12899985 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6123471 [patent_doc_number] => 20110085397 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'Semiconductor device and information processing system including the same' [patent_app_type] => utility [patent_app_number] => 12/923749 [patent_app_country] => US [patent_app_date] => 2010-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10824 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20110085397.pdf [firstpage_image] =>[orig_patent_app_number] => 12923749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8471291 [patent_doc_number] => 08300480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-30 [patent_title] => 'Semiconductor device having sense amplifiers supplied with an over-drive voltage in a normal mode and supplied with a step-down voltage in a refresh mode' [patent_app_type] => utility [patent_app_number] => 12/897399 [patent_app_country] => US [patent_app_date] => 2010-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 10647 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12897399 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7732233 [patent_doc_number] => 08102697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Three-dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array' [patent_app_type] => utility [patent_app_number] => 12/896392 [patent_app_country] => US [patent_app_date] => 2010-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 30 [patent_no_of_words] => 11707 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/102/08102697.pdf [firstpage_image] =>[orig_patent_app_number] => 12896392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8052393 [patent_doc_number] => 20120075930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-29 [patent_title] => 'REUSE OF INFORMATION FROM MEMORY READ OPERATIONS' [patent_app_type] => utility [patent_app_number] => 12/891475 [patent_app_country] => US [patent_app_date] => 2010-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8264 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0075/20120075930.pdf [firstpage_image] =>[orig_patent_app_number] => 12891475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8739743 [patent_doc_number] => 08411523 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-02 [patent_title] => 'Reduced current requirements for DRAM self-refresh modes via staggered refresh operations of subsets of memory banks or rows' [patent_app_type] => utility [patent_app_number] => 12/890083 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2896 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12890083 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5991809 [patent_doc_number] => 20110013462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'Method for Operating Memory' [patent_app_type] => utility [patent_app_number] => 12/889710 [patent_app_country] => US [patent_app_date] => 2010-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3612 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20110013462.pdf [firstpage_image] =>[orig_patent_app_number] => 12889710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5974476 [patent_doc_number] => 20110069540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'Method of a phase-change memory programming' [patent_app_type] => utility [patent_app_number] => 12/924167 [patent_app_country] => US [patent_app_date] => 2010-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2841 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20110069540.pdf [firstpage_image] =>[orig_patent_app_number] => 12924167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6374903 [patent_doc_number] => 20100315894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'Low Power Sensing In a Multi-Port Sram Using Pre-Discharged Bit Lines' [patent_app_type] => utility [patent_app_number] => 12/861026 [patent_app_country] => US [patent_app_date] => 2010-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3872 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20100315894.pdf [firstpage_image] =>[orig_patent_app_number] => 12861026 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4605588 [patent_doc_number] => 07986571 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'Low power, single-ended sensing in a multi-port SRAM using pre-discharged bit lines' [patent_app_type] => utility [patent_app_number] => 12/858499 [patent_app_country] => US [patent_app_date] => 2010-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4827 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/986/07986571.pdf [firstpage_image] =>[orig_patent_app_number] => 12858499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6385206 [patent_doc_number] => 20100302882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'Random Access Memory for Use in an Emulation Environment' [patent_app_type] => utility [patent_app_number] => 12/854747 [patent_app_country] => US [patent_app_date] => 2010-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3840 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20100302882.pdf [firstpage_image] =>[orig_patent_app_number] => 12854747 [rel_patent_id] =>[rel_patent_doc_number] =>)