Search

Andrew Q. Tran

Examiner (ID: 7081)

Most Active Art Unit
2824
Art Unit(s)
2511, 2812, 2818, 2824, 2825, 2827
Total Applications
1878
Issued Applications
1746
Pending Applications
27
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6384926 [patent_doc_number] => 20100302844 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'METHOD AND APPARATUS FOR PROVIDING A NON-VOLATILE MEMORY WITH REDUCED CELL CAPACITIVE COUPLING' [patent_app_type] => utility [patent_app_number] => 12/818565 [patent_app_country] => US [patent_app_date] => 2010-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3112 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20100302844.pdf [firstpage_image] =>[orig_patent_app_number] => 12818565 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/818565
Method and apparatus for providing a non-volatile memory with reduced cell capacitive coupling Jun 17, 2010 Issued
Array ( [id] => 4438803 [patent_doc_number] => 07898870 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Nonvolatile memory device having a bit line select voltage generator adapted to a temperature change' [patent_app_type] => utility [patent_app_number] => 12/790579 [patent_app_country] => US [patent_app_date] => 2010-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4199 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/898/07898870.pdf [firstpage_image] =>[orig_patent_app_number] => 12790579 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/790579
Nonvolatile memory device having a bit line select voltage generator adapted to a temperature change May 27, 2010 Issued
Array ( [id] => 4438921 [patent_doc_number] => 07898901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Method for controlling clock cycle time for reduced power consumption in a semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/790607 [patent_app_country] => US [patent_app_date] => 2010-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 4489 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/898/07898901.pdf [firstpage_image] =>[orig_patent_app_number] => 12790607 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/790607
Method for controlling clock cycle time for reduced power consumption in a semiconductor memory device May 27, 2010 Issued
Array ( [id] => 4571361 [patent_doc_number] => 07839702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-23 [patent_title] => 'Three-dimensional non-volatile register with an oxygen-ion-based memory element and a vertically-stacked register logic' [patent_app_type] => utility [patent_app_number] => 12/800289 [patent_app_country] => US [patent_app_date] => 2010-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3679 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/839/07839702.pdf [firstpage_image] =>[orig_patent_app_number] => 12800289 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/800289
Three-dimensional non-volatile register with an oxygen-ion-based memory element and a vertically-stacked register logic May 10, 2010 Issued
Array ( [id] => 6520510 [patent_doc_number] => 20100220543 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'Circuitry and method for indicating a memory' [patent_app_type] => utility [patent_app_number] => 12/800088 [patent_app_country] => US [patent_app_date] => 2010-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 8761 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20100220543.pdf [firstpage_image] =>[orig_patent_app_number] => 12800088 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/800088
Circuitry and method for indicating a memory May 5, 2010 Issued
Array ( [id] => 8423176 [patent_doc_number] => 08279667 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'Integrated circuit memory systems and program methods thereof including a magnetic track memory array using magnetic domain wall movement' [patent_app_type] => utility [patent_app_number] => 12/775133 [patent_app_country] => US [patent_app_date] => 2010-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 9348 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12775133 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/775133
Integrated circuit memory systems and program methods thereof including a magnetic track memory array using magnetic domain wall movement May 5, 2010 Issued
Array ( [id] => 4503817 [patent_doc_number] => 07948795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Thin film magnetic memory device including memory cells having a magnetic tunnel junction' [patent_app_type] => utility [patent_app_number] => 12/772910 [patent_app_country] => US [patent_app_date] => 2010-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 73 [patent_figures_cnt] => 92 [patent_no_of_words] => 43738 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/948/07948795.pdf [firstpage_image] =>[orig_patent_app_number] => 12772910 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/772910
Thin film magnetic memory device including memory cells having a magnetic tunnel junction May 2, 2010 Issued
Array ( [id] => 7572213 [patent_doc_number] => 20110267869 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-03 [patent_title] => 'CIRCUIT FOR VERIFYING THE WRITE ENABLE OF A ONE TIME PROGRAMMABLE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/771209 [patent_app_country] => US [patent_app_date] => 2010-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5909 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20110267869.pdf [firstpage_image] =>[orig_patent_app_number] => 12771209 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/771209
Circuit for verifying the write enable of a one time programmable memory Apr 29, 2010 Issued
Array ( [id] => 8423200 [patent_doc_number] => 08279691 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'Semiconductor memory integrated device with a precharge circuit having thin-film transistors gated by a voltage higher than a power supply voltage' [patent_app_type] => utility [patent_app_number] => 12/769141 [patent_app_country] => US [patent_app_date] => 2010-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 9047 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12769141 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/769141
Semiconductor memory integrated device with a precharge circuit having thin-film transistors gated by a voltage higher than a power supply voltage Apr 27, 2010 Issued
Array ( [id] => 6233402 [patent_doc_number] => 20100265754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND DATA PROCESSING DEVICE' [patent_app_type] => utility [patent_app_number] => 12/759725 [patent_app_country] => US [patent_app_date] => 2010-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 18982 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20100265754.pdf [firstpage_image] =>[orig_patent_app_number] => 12759725 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/759725
Semiconductor memory device capable of optimizing an operation time of a boosting circuit during a writing period Apr 13, 2010 Issued
Array ( [id] => 6316426 [patent_doc_number] => 20100195367 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'NONVOLATILE MEMORY AND WRITING METHOD THEREOF, AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/756342 [patent_app_country] => US [patent_app_date] => 2010-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 17405 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20100195367.pdf [firstpage_image] =>[orig_patent_app_number] => 12756342 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/756342
Write-once nonvolatile memory with redundancy capability Apr 7, 2010 Issued
Array ( [id] => 6385217 [patent_doc_number] => 20100302884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'Method of preventing coupling noises for a non-volatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/662247 [patent_app_country] => US [patent_app_date] => 2010-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10658 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20100302884.pdf [firstpage_image] =>[orig_patent_app_number] => 12662247 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/662247
Method of preventing coupling noises for a non-volatile semiconductor memory device Apr 6, 2010 Issued
Array ( [id] => 6494973 [patent_doc_number] => 20100259998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-14 [patent_title] => 'Non-volatile RAM, and solid state drive and computer system including the same' [patent_app_type] => utility [patent_app_number] => 12/662221 [patent_app_country] => US [patent_app_date] => 2010-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4887 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20100259998.pdf [firstpage_image] =>[orig_patent_app_number] => 12662221 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/662221
Non-volatile random access memory with a control circuit for preventing an initial resistance failure, a solid state drive, and a computer system including the same Apr 5, 2010 Issued
Array ( [id] => 8447720 [patent_doc_number] => 08289779 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Memory cell sensing device equipped with a ramp voltage generator using a digital-to-analog converter (DAC) and counters, and sensing methods thereof' [patent_app_type] => utility [patent_app_number] => 12/751575 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7196 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12751575 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/751575
Memory cell sensing device equipped with a ramp voltage generator using a digital-to-analog converter (DAC) and counters, and sensing methods thereof Mar 30, 2010 Issued
Array ( [id] => 8234132 [patent_doc_number] => 08199576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-12 [patent_title] => 'Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a double-global-bit-line architecture' [patent_app_type] => utility [patent_app_number] => 12/748233 [patent_app_country] => US [patent_app_date] => 2010-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 20770 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/199/08199576.pdf [firstpage_image] =>[orig_patent_app_number] => 12748233 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/748233
Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a double-global-bit-line architecture Mar 25, 2010 Issued
Array ( [id] => 6390880 [patent_doc_number] => 20100177569 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'SINGLE POLY EEPROM ALLOWING CONTINUOUS ADJUSTMENT OF ITS THRESHOLD VOLTAGE' [patent_app_type] => utility [patent_app_number] => 12/731951 [patent_app_country] => US [patent_app_date] => 2010-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5280 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20100177569.pdf [firstpage_image] =>[orig_patent_app_number] => 12731951 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/731951
SINGLE POLY EEPROM ALLOWING CONTINUOUS ADJUSTMENT OF ITS THRESHOLD VOLTAGE Mar 24, 2010 Abandoned
Array ( [id] => 9061323 [patent_doc_number] => 08547766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-01 [patent_title] => 'Area-efficient data line layouts to suppress the degradation of electrical characteristics' [patent_app_type] => utility [patent_app_number] => 12/659883 [patent_app_country] => US [patent_app_date] => 2010-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4069 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12659883 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/659883
Area-efficient data line layouts to suppress the degradation of electrical characteristics Mar 23, 2010 Issued
Array ( [id] => 6227705 [patent_doc_number] => 20100182853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'Semiconductor Memory Device Having a Floating Storage Bulk Region Capable of Holding/Emitting Excessive Majority Carriers' [patent_app_type] => utility [patent_app_number] => 12/725796 [patent_app_country] => US [patent_app_date] => 2010-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 54 [patent_figures_cnt] => 54 [patent_no_of_words] => 20625 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20100182853.pdf [firstpage_image] =>[orig_patent_app_number] => 12725796 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/725796
Semiconductor memory device having a floating storage bulk region capable of holding/emitting excessive majority carriers Mar 16, 2010 Issued
Array ( [id] => 7732297 [patent_doc_number] => 08102729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Resistive memory device capable of compensating for variations of bit line resistances' [patent_app_type] => utility [patent_app_number] => 12/659689 [patent_app_country] => US [patent_app_date] => 2010-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5888 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/102/08102729.pdf [firstpage_image] =>[orig_patent_app_number] => 12659689 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/659689
Resistive memory device capable of compensating for variations of bit line resistances Mar 16, 2010 Issued
Array ( [id] => 6618080 [patent_doc_number] => 20100172175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'MEMORY DEVICE AND METHOD HAVING CHARGE LEVEL ASSIGNMENTS SELECTED TO MINIMIZE SIGNAL COUPLING' [patent_app_type] => utility [patent_app_number] => 12/724219 [patent_app_country] => US [patent_app_date] => 2010-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6306 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20100172175.pdf [firstpage_image] =>[orig_patent_app_number] => 12724219 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/724219
Memory device and method having charge level assignments selected to minimize signal coupling Mar 14, 2010 Issued
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