Search

Andrew Q. Tran

Examiner (ID: 7081)

Most Active Art Unit
2824
Art Unit(s)
2511, 2812, 2818, 2824, 2825, 2827
Total Applications
1878
Issued Applications
1746
Pending Applications
27
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6403707 [patent_doc_number] => 20100165741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'DYNAMIC PASS VOLTAGE' [patent_app_type] => utility [patent_app_number] => 12/721693 [patent_app_country] => US [patent_app_date] => 2010-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8043 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20100165741.pdf [firstpage_image] =>[orig_patent_app_number] => 12721693 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/721693
Memory device with a decreasing dynamic pass voltage for reducing read-disturb effect Mar 10, 2010 Issued
Array ( [id] => 6403484 [patent_doc_number] => 20100165706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'STATIC MEMORY CELL HAVING INDEPENDENT DATA HOLDING VOLTAGE' [patent_app_type] => utility [patent_app_number] => 12/722222 [patent_app_country] => US [patent_app_date] => 2010-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13292 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20100165706.pdf [firstpage_image] =>[orig_patent_app_number] => 12722222 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/722222
Static memory cell having independent data holding voltage Mar 10, 2010 Issued
Array ( [id] => 7754114 [patent_doc_number] => 08111563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => 'Multi-level nonvolatile memory device with fast execution of program speed and programming method of the same' [patent_app_type] => utility [patent_app_number] => 12/659473 [patent_app_country] => US [patent_app_date] => 2010-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 6842 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/111/08111563.pdf [firstpage_image] =>[orig_patent_app_number] => 12659473 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/659473
Multi-level nonvolatile memory device with fast execution of program speed and programming method of the same Mar 9, 2010 Issued
Array ( [id] => 4465031 [patent_doc_number] => 07881116 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Nonvolatile semiconductor memory capable of trimming an initial program voltage for each word line' [patent_app_type] => utility [patent_app_number] => 12/719550 [patent_app_country] => US [patent_app_date] => 2010-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11176 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/881/07881116.pdf [firstpage_image] =>[orig_patent_app_number] => 12719550 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/719550
Nonvolatile semiconductor memory capable of trimming an initial program voltage for each word line Mar 7, 2010 Issued
Array ( [id] => 6520486 [patent_doc_number] => 20100220540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE CAPABLE OF DRIVING NON-SELECTED WORD LINES TO FIRST AND SECOND POTENTIALS' [patent_app_type] => utility [patent_app_number] => 12/718808 [patent_app_country] => US [patent_app_date] => 2010-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 58 [patent_no_of_words] => 25283 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0220/20100220540.pdf [firstpage_image] =>[orig_patent_app_number] => 12718808 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/718808
SEMICONDUCTOR MEMORY DEVICE CAPABLE OF DRIVING NON-SELECTED WORD LINES TO FIRST AND SECOND POTENTIALS Mar 4, 2010 Abandoned
Array ( [id] => 6587953 [patent_doc_number] => 20100321983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE CAPABLE OF DRIVING NON-SELECTED WORD LINES TO FIRST AND SECOND POTENTIALS' [patent_app_type] => utility [patent_app_number] => 12/718819 [patent_app_country] => US [patent_app_date] => 2010-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 58 [patent_figures_cnt] => 58 [patent_no_of_words] => 25291 [patent_no_of_claims] => 98 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0321/20100321983.pdf [firstpage_image] =>[orig_patent_app_number] => 12718819 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/718819
SEMICONDUCTOR MEMORY DEVICE CAPABLE OF DRIVING NON-SELECTED WORD LINES TO FIRST AND SECOND POTENTIALS Mar 4, 2010 Abandoned
Array ( [id] => 6627910 [patent_doc_number] => 20100226168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-09 [patent_title] => 'Programming methods for phase-change memory' [patent_app_type] => utility [patent_app_number] => 12/660783 [patent_app_country] => US [patent_app_date] => 2010-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7614 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0226/20100226168.pdf [firstpage_image] =>[orig_patent_app_number] => 12660783 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/660783
Programming methods for phase-change memory Mar 2, 2010 Abandoned
Array ( [id] => 7528800 [patent_doc_number] => 08045404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-25 [patent_title] => 'Semiconductor memory device capable of preventing damage to a bitline during a data masking operation' [patent_app_type] => utility [patent_app_number] => 12/660439 [patent_app_country] => US [patent_app_date] => 2010-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4110 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/045/08045404.pdf [firstpage_image] =>[orig_patent_app_number] => 12660439 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/660439
Semiconductor memory device capable of preventing damage to a bitline during a data masking operation Feb 25, 2010 Issued
Array ( [id] => 6491897 [patent_doc_number] => 20100214858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'Delay locked loop circuit for preventing failure of coarse locking' [patent_app_type] => utility [patent_app_number] => 12/659057 [patent_app_country] => US [patent_app_date] => 2010-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4542 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20100214858.pdf [firstpage_image] =>[orig_patent_app_number] => 12659057 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/659057
Delay locked loop circuit for preventing failure of coarse locking Feb 23, 2010 Issued
Array ( [id] => 6571494 [patent_doc_number] => 20100290303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-18 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/656859 [patent_app_country] => US [patent_app_date] => 2010-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4396 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0290/20100290303.pdf [firstpage_image] =>[orig_patent_app_number] => 12656859 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/656859
Semiconductor electrically programmable fuse (eFuse) having a polysilicon layer not doped with an impurity ion and a programming method thereof Feb 17, 2010 Issued
Array ( [id] => 6483966 [patent_doc_number] => 20100208525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/697505 [patent_app_country] => US [patent_app_date] => 2010-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5651 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20100208525.pdf [firstpage_image] =>[orig_patent_app_number] => 12697505 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/697505
Non-volatile semiconductor memory device with a sense amplifier reference circuit having a MONOS transfer transistor Jan 31, 2010 Issued
Array ( [id] => 6316616 [patent_doc_number] => 20100195418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-05 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/697543 [patent_app_country] => US [patent_app_date] => 2010-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8501 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20100195418.pdf [firstpage_image] =>[orig_patent_app_number] => 12697543 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/697543
Semiconductor memory device and system capable of executing an interleave programming for a plurality of memory chips and a 2-plane programming at the respective memory chips Jan 31, 2010 Issued
Array ( [id] => 6227648 [patent_doc_number] => 20100182829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/691293 [patent_app_country] => US [patent_app_date] => 2010-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6843 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20100182829.pdf [firstpage_image] =>[orig_patent_app_number] => 12691293 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/691293
Semiconductor memory device with a write control circuit commonly provided for a plurality of pages Jan 20, 2010 Issued
Array ( [id] => 4467973 [patent_doc_number] => 07936630 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-05-03 [patent_title] => 'Method and apparatus for calibrating a read/write channel in a memory arrangement' [patent_app_type] => utility [patent_app_number] => 12/689891 [patent_app_country] => US [patent_app_date] => 2010-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3449 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/936/07936630.pdf [firstpage_image] =>[orig_patent_app_number] => 12689891 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/689891
Method and apparatus for calibrating a read/write channel in a memory arrangement Jan 18, 2010 Issued
Array ( [id] => 6172820 [patent_doc_number] => 20110176369 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-21 [patent_title] => 'ERASE VERIFICATION METHOD OF FLASH MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/689235 [patent_app_country] => US [patent_app_date] => 2010-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2972 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20110176369.pdf [firstpage_image] =>[orig_patent_app_number] => 12689235 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/689235
Erase verification method of flash memory by selectively assigning deselected sectors Jan 18, 2010 Issued
Array ( [id] => 7777225 [patent_doc_number] => 08120939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'ROM cell having an isolation transistor formed between first and second pass transistors and connected between a differential bitline pair' [patent_app_type] => utility [patent_app_number] => 12/689373 [patent_app_country] => US [patent_app_date] => 2010-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/120/08120939.pdf [firstpage_image] =>[orig_patent_app_number] => 12689373 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/689373
ROM cell having an isolation transistor formed between first and second pass transistors and connected between a differential bitline pair Jan 18, 2010 Issued
Array ( [id] => 7765498 [patent_doc_number] => 08116149 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Circuit and method for small swing memory signals' [patent_app_type] => utility [patent_app_number] => 12/687571 [patent_app_country] => US [patent_app_date] => 2010-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7957 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/116/08116149.pdf [firstpage_image] =>[orig_patent_app_number] => 12687571 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/687571
Circuit and method for small swing memory signals Jan 13, 2010 Issued
Array ( [id] => 6227712 [patent_doc_number] => 20100182858 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-22 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PROGRAMMING' [patent_app_type] => utility [patent_app_number] => 12/685939 [patent_app_country] => US [patent_app_date] => 2010-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7857 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20100182858.pdf [firstpage_image] =>[orig_patent_app_number] => 12685939 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/685939
Nonvolatile semiconductor memory device capable of preventing write-disturb and method of programming Jan 11, 2010 Issued
Array ( [id] => 7715199 [patent_doc_number] => 08094512 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-10 [patent_title] => 'Semiconductor memory device with individual and selective refresh of data storage banks' [patent_app_type] => utility [patent_app_number] => 12/685245 [patent_app_country] => US [patent_app_date] => 2010-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/094/08094512.pdf [firstpage_image] =>[orig_patent_app_number] => 12685245 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/685245
Semiconductor memory device with individual and selective refresh of data storage banks Jan 10, 2010 Issued
Array ( [id] => 6390891 [patent_doc_number] => 20100177572 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'SEMICONDUCTOR DEVICE CAPABLE OF ADJUSTING PAGE SIZE' [patent_app_type] => utility [patent_app_number] => 12/684497 [patent_app_country] => US [patent_app_date] => 2010-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7863 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0177/20100177572.pdf [firstpage_image] =>[orig_patent_app_number] => 12684497 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/684497
Semiconductor device capable of adjusting memory page size based on a row address and a bank address Jan 7, 2010 Issued
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