Search

Andrew Q. Tran

Examiner (ID: 7081)

Most Active Art Unit
2824
Art Unit(s)
2511, 2812, 2818, 2824, 2825, 2827
Total Applications
1878
Issued Applications
1746
Pending Applications
27
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5974505 [patent_doc_number] => 20110069552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DATA READ THEREIN' [patent_app_type] => utility [patent_app_number] => 12/684349 [patent_app_country] => US [patent_app_date] => 2010-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 14518 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20110069552.pdf [firstpage_image] =>[orig_patent_app_number] => 12684349 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/684349
Three-dimensional nonvolatile semiconductor memory device for curbing a leak current and method of data read therein Jan 7, 2010 Issued
Array ( [id] => 8593413 [patent_doc_number] => 08351289 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-01-08 [patent_title] => 'Apparatuses and methods for sensing a phase-change test cell and determining changes to the test cell resistance due to thermal exposure' [patent_app_type] => utility [patent_app_number] => 12/655377 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2721 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12655377 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/655377
Apparatuses and methods for sensing a phase-change test cell and determining changes to the test cell resistance due to thermal exposure Dec 29, 2009 Issued
Array ( [id] => 8365121 [patent_doc_number] => 08254190 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-28 [patent_title] => 'System and method for driving a memory circuit utilizing a pull-up resistance when strobing the memory circuit and driving the memory circuit devoid of the pull-up resistance when reading or writing data' [patent_app_type] => utility [patent_app_number] => 12/649223 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2648 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12649223 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/649223
System and method for driving a memory circuit utilizing a pull-up resistance when strobing the memory circuit and driving the memory circuit devoid of the pull-up resistance when reading or writing data Dec 28, 2009 Issued
Array ( [id] => 7546688 [patent_doc_number] => 08054665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Stacked memory device including a pre-decoder/pre-driver sandwiched between a plurality of inter-decoders/inter-drivers' [patent_app_type] => utility [patent_app_number] => 12/654645 [patent_app_country] => US [patent_app_date] => 2009-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 4181 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/054/08054665.pdf [firstpage_image] =>[orig_patent_app_number] => 12654645 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/654645
Stacked memory device including a pre-decoder/pre-driver sandwiched between a plurality of inter-decoders/inter-drivers Dec 27, 2009 Issued
Array ( [id] => 4601701 [patent_doc_number] => 07978540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Extraction of a binary code based on physical parameters of an integrated circuit via programming resistors' [patent_app_type] => utility [patent_app_number] => 12/641789 [patent_app_country] => US [patent_app_date] => 2009-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 11429 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/978/07978540.pdf [firstpage_image] =>[orig_patent_app_number] => 12641789 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/641789
Extraction of a binary code based on physical parameters of an integrated circuit via programming resistors Dec 17, 2009 Issued
Array ( [id] => 7546716 [patent_doc_number] => 08054693 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-08 [patent_title] => 'Capacitorless dynamic memory device capable of performing data read/restoration and method for operating the same' [patent_app_type] => utility [patent_app_number] => 12/654283 [patent_app_country] => US [patent_app_date] => 2009-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9094 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/054/08054693.pdf [firstpage_image] =>[orig_patent_app_number] => 12654283 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/654283
Capacitorless dynamic memory device capable of performing data read/restoration and method for operating the same Dec 15, 2009 Issued
Array ( [id] => 8191900 [patent_doc_number] => 08184480 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-22 [patent_title] => 'Multi-level nonvolatile memory device with reduced number of read voltages based on a cell address and method for operating the same' [patent_app_type] => utility [patent_app_number] => 12/654063 [patent_app_country] => US [patent_app_date] => 2009-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/184/08184480.pdf [firstpage_image] =>[orig_patent_app_number] => 12654063 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/654063
Multi-level nonvolatile memory device with reduced number of read voltages based on a cell address and method for operating the same Dec 8, 2009 Issued
Array ( [id] => 6602483 [patent_doc_number] => 20100309709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'UNIT CELL OF NONVOLATILE MEMORY DEVICE AND NONVOLATILE MEMORY DEVICE WITH THE SAME' [patent_app_type] => utility [patent_app_number] => 12/609369 [patent_app_country] => US [patent_app_date] => 2009-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7858 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0309/20100309709.pdf [firstpage_image] =>[orig_patent_app_number] => 12609369 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/609369
Antifuse unit cell of nonvolatile memory device for enhancing data sense margin and nonvolatile memory device with the same Oct 29, 2009 Issued
Array ( [id] => 8691554 [patent_doc_number] => 08391085 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Semiconductor memory device capable of matching the timing between sub-amplifier control signal and column selection signal' [patent_app_type] => utility [patent_app_number] => 12/605755 [patent_app_country] => US [patent_app_date] => 2009-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7027 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12605755 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/605755
Semiconductor memory device capable of matching the timing between sub-amplifier control signal and column selection signal Oct 25, 2009 Issued
Array ( [id] => 6123463 [patent_doc_number] => 20110085392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'METHOD FOR WRITING DATA TO MEMORY ARRAY' [patent_app_type] => utility [patent_app_number] => 12/578917 [patent_app_country] => US [patent_app_date] => 2009-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5829 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20110085392.pdf [firstpage_image] =>[orig_patent_app_number] => 12578917 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/578917
Method of increasing a timing margin for writing data to a memory array Oct 13, 2009 Issued
Array ( [id] => 6535438 [patent_doc_number] => 20100232055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'Information storage devices and methods of operating the same' [patent_app_type] => utility [patent_app_number] => 12/588333 [patent_app_country] => US [patent_app_date] => 2009-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 18162 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20100232055.pdf [firstpage_image] =>[orig_patent_app_number] => 12588333 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/588333
Magnetic storage device having a buffer track and storage tracks, and method of operating the same Oct 12, 2009 Issued
Array ( [id] => 6249676 [patent_doc_number] => 20100027333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'Nonvolatile Semiconductor Memory Device' [patent_app_type] => utility [patent_app_number] => 12/576638 [patent_app_country] => US [patent_app_date] => 2009-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 44 [patent_no_of_words] => 19018 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20100027333.pdf [firstpage_image] =>[orig_patent_app_number] => 12576638 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/576638
Nonvolatile semiconductor memory device with first and second write sequences controlled by a command or an address Oct 8, 2009 Issued
Array ( [id] => 7507164 [patent_doc_number] => 08036034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-11 [patent_title] => 'Semiconductor storage device equipped with a sense amplifier for reading data and threshold-voltage-information data' [patent_app_type] => utility [patent_app_number] => 12/564425 [patent_app_country] => US [patent_app_date] => 2009-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 11495 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/036/08036034.pdf [firstpage_image] =>[orig_patent_app_number] => 12564425 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/564425
Semiconductor storage device equipped with a sense amplifier for reading data and threshold-voltage-information data Sep 21, 2009 Issued
Array ( [id] => 6474814 [patent_doc_number] => 20100008148 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-14 [patent_title] => 'Low Noise Sense Amplifier Array and Method for Nonvolatile Memory' [patent_app_type] => utility [patent_app_number] => 12/563918 [patent_app_country] => US [patent_app_date] => 2009-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12302 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20100008148.pdf [firstpage_image] =>[orig_patent_app_number] => 12563918 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/563918
Low noise sense amplifier array and method for nonvolatile memory Sep 20, 2009 Issued
Array ( [id] => 4584406 [patent_doc_number] => 07826249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Three dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array' [patent_app_type] => utility [patent_app_number] => 12/559178 [patent_app_country] => US [patent_app_date] => 2009-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 30 [patent_no_of_words] => 11683 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/826/07826249.pdf [firstpage_image] =>[orig_patent_app_number] => 12559178 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/559178
Three dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array Sep 13, 2009 Issued
Array ( [id] => 4474568 [patent_doc_number] => 07944735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-17 [patent_title] => 'Method of making a nanotube-based shadow random access memory' [patent_app_type] => utility [patent_app_number] => 12/550975 [patent_app_country] => US [patent_app_date] => 2009-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4936 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/944/07944735.pdf [firstpage_image] =>[orig_patent_app_number] => 12550975 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/550975
Method of making a nanotube-based shadow random access memory Aug 30, 2009 Issued
Array ( [id] => 4605589 [patent_doc_number] => 07986572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-26 [patent_title] => 'Magnetic memory capable of minimizing gate voltage stress in unselected memory cells' [patent_app_type] => utility [patent_app_number] => 12/583255 [patent_app_country] => US [patent_app_date] => 2009-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2825 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/986/07986572.pdf [firstpage_image] =>[orig_patent_app_number] => 12583255 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/583255
Magnetic memory capable of minimizing gate voltage stress in unselected memory cells Aug 16, 2009 Issued
Array ( [id] => 4577112 [patent_doc_number] => 07848140 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-07 [patent_title] => 'Flash memory array system including a top gate memory cell' [patent_app_type] => utility [patent_app_number] => 12/507783 [patent_app_country] => US [patent_app_date] => 2009-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 10228 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/848/07848140.pdf [firstpage_image] =>[orig_patent_app_number] => 12507783 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/507783
Flash memory array system including a top gate memory cell Jul 21, 2009 Issued
Array ( [id] => 8803555 [patent_doc_number] => 08441834 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Resistive memory element sensing using averaging' [patent_app_type] => utility [patent_app_number] => 12/504851 [patent_app_country] => US [patent_app_date] => 2009-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3712 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12504851 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/504851
Resistive memory element sensing using averaging Jul 16, 2009 Issued
Array ( [id] => 4584515 [patent_doc_number] => 07826266 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Semiconductor device having global and local data lines coupled to memory mats' [patent_app_type] => utility [patent_app_number] => 12/498911 [patent_app_country] => US [patent_app_date] => 2009-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 9967 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/826/07826266.pdf [firstpage_image] =>[orig_patent_app_number] => 12498911 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/498911
Semiconductor device having global and local data lines coupled to memory mats Jul 6, 2009 Issued
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