Search

Andrew Q. Tran

Examiner (ID: 7081)

Most Active Art Unit
2824
Art Unit(s)
2511, 2812, 2818, 2824, 2825, 2827
Total Applications
1878
Issued Applications
1746
Pending Applications
27
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 5463248 [patent_doc_number] => 20090323448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-31 [patent_title] => 'Bias Sensing in Dram Sense Amplifiers Through Voltage-Coupling/Decoupling Device' [patent_app_type] => utility [patent_app_number] => 12/498541 [patent_app_country] => US [patent_app_date] => 2009-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7414 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0323/20090323448.pdf [firstpage_image] =>[orig_patent_app_number] => 12498541 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/498541
Bias sensing in DRAM sense amplifiers through voltage-coupling/decoupling device Jul 6, 2009 Issued
Array ( [id] => 8376713 [patent_doc_number] => 08259515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-04 [patent_title] => 'Circuitry for reading phase-change memory cells having a clamping circuit' [patent_app_type] => utility [patent_app_number] => 12/491352 [patent_app_country] => US [patent_app_date] => 2009-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7821 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12491352 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/491352
Circuitry for reading phase-change memory cells having a clamping circuit Jun 24, 2009 Issued
Array ( [id] => 6462562 [patent_doc_number] => 20100281227 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'MULTI-PORT MEMORY DEVICES AND METHODS' [patent_app_type] => utility [patent_app_number] => 12/432610 [patent_app_country] => US [patent_app_date] => 2009-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3198 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20100281227.pdf [firstpage_image] =>[orig_patent_app_number] => 12432610 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/432610
Configurable multi-port memory devices and methods Apr 28, 2009 Issued
Array ( [id] => 6462610 [patent_doc_number] => 20100281231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'HIERARCHICAL MEMORY ARBITRATION TECHNIQUE FOR DISPARATE SOURCES' [patent_app_type] => utility [patent_app_number] => 12/431874 [patent_app_country] => US [patent_app_date] => 2009-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4906 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20100281231.pdf [firstpage_image] =>[orig_patent_app_number] => 12431874 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/431874
Hierarchical memory arbitration technique for disparate sources Apr 28, 2009 Issued
Array ( [id] => 8109261 [patent_doc_number] => 08156290 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-04-10 [patent_title] => 'Just-in-time continuous segment cleaning' [patent_app_type] => utility [patent_app_number] => 12/429108 [patent_app_country] => US [patent_app_date] => 2009-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4922 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/156/08156290.pdf [firstpage_image] =>[orig_patent_app_number] => 12429108 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/429108
Just-in-time continuous segment cleaning Apr 22, 2009 Issued
Array ( [id] => 6616753 [patent_doc_number] => 20100049936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'MEMORY ACCESS CONTROL DEVICE AND CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/428486 [patent_app_country] => US [patent_app_date] => 2009-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5804 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20100049936.pdf [firstpage_image] =>[orig_patent_app_number] => 12428486 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/428486
Memory access control device equipped with memory access request generating modules/arbitrator and control method thereof Apr 22, 2009 Issued
Array ( [id] => 5433991 [patent_doc_number] => 20090168577 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-02 [patent_title] => 'SEMICONDUCTOR STORAGE DEVICE, AND DATA READING METHOD' [patent_app_type] => utility [patent_app_number] => 12/398816 [patent_app_country] => US [patent_app_date] => 2009-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7315 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0168/20090168577.pdf [firstpage_image] =>[orig_patent_app_number] => 12398816 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/398816
SEMICONDUCTOR STORAGE DEVICE, AND DATA READING METHOD Mar 4, 2009 Abandoned
Array ( [id] => 104640 [patent_doc_number] => 07729197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-01 [patent_title] => 'Memory device having a delay locked loop with frequency control' [patent_app_type] => utility [patent_app_number] => 12/368148 [patent_app_country] => US [patent_app_date] => 2009-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 4464 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/729/07729197.pdf [firstpage_image] =>[orig_patent_app_number] => 12368148 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/368148
Memory device having a delay locked loop with frequency control Feb 8, 2009 Issued
Array ( [id] => 5277035 [patent_doc_number] => 20090129167 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'SEMICONDUCTOR MAGNETIC MEMORY INTEGRATING A MAGNETIC TUNNELING JUNCTION ABOVE A FLOATING-GATE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 12/360496 [patent_app_country] => US [patent_app_date] => 2009-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5328 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20090129167.pdf [firstpage_image] =>[orig_patent_app_number] => 12360496 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/360496
Semiconductor magnetic memory integrating a magnetic tunneling junction above a floating-gate memory cell Jan 26, 2009 Issued
Array ( [id] => 5341675 [patent_doc_number] => 20090180325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-16 [patent_title] => 'Partitioned Erase And Erase Verification In Non-Volatile Memory' [patent_app_type] => utility [patent_app_number] => 12/358633 [patent_app_country] => US [patent_app_date] => 2009-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 17691 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20090180325.pdf [firstpage_image] =>[orig_patent_app_number] => 12358633 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/358633
Methods for partitioned erase and erase verification in non-volatile memory to compensate for capacitive coupling effects Jan 22, 2009 Issued
Array ( [id] => 5263624 [patent_doc_number] => 20090116309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-07 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/348306 [patent_app_country] => US [patent_app_date] => 2009-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 19325 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20090116309.pdf [firstpage_image] =>[orig_patent_app_number] => 12348306 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/348306
SEMICONDUCTOR DEVICE Jan 3, 2009 Abandoned
Array ( [id] => 7594602 [patent_doc_number] => 07626861 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-01 [patent_title] => 'Employing unused configuration memory cells as scratchpad memory' [patent_app_type] => utility [patent_app_number] => 12/343417 [patent_app_country] => US [patent_app_date] => 2008-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6640 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/626/07626861.pdf [firstpage_image] =>[orig_patent_app_number] => 12343417 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/343417
Employing unused configuration memory cells as scratchpad memory Dec 22, 2008 Issued
Array ( [id] => 7715136 [patent_doc_number] => 08094485 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-10 [patent_title] => 'Variable resistance nonvolatile storage device with oxygen-deficient oxide layer and asymmetric substrate bias effect' [patent_app_type] => utility [patent_app_number] => 12/676933 [patent_app_country] => US [patent_app_date] => 2008-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 21646 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/094/08094485.pdf [firstpage_image] =>[orig_patent_app_number] => 12676933 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/676933
Variable resistance nonvolatile storage device with oxygen-deficient oxide layer and asymmetric substrate bias effect Dec 14, 2008 Issued
Array ( [id] => 4435881 [patent_doc_number] => 07969777 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-28 [patent_title] => 'Thyristor-based memory array having lines with standby voltages' [patent_app_type] => utility [patent_app_number] => 12/326027 [patent_app_country] => US [patent_app_date] => 2008-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 3748 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/969/07969777.pdf [firstpage_image] =>[orig_patent_app_number] => 12326027 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/326027
Thyristor-based memory array having lines with standby voltages Nov 30, 2008 Issued
Array ( [id] => 55552 [patent_doc_number] => 07773415 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Flash memory device capable of preventing soft-programming during a read operation and reading method thereof' [patent_app_type] => utility [patent_app_number] => 12/292741 [patent_app_country] => US [patent_app_date] => 2008-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5519 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/773/07773415.pdf [firstpage_image] =>[orig_patent_app_number] => 12292741 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/292741
Flash memory device capable of preventing soft-programming during a read operation and reading method thereof Nov 24, 2008 Issued
Array ( [id] => 76592 [patent_doc_number] => 07751252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-06 [patent_title] => 'Semiconductor memory with a reference current generating circuit having a reference current generating section and an amplifier section' [patent_app_type] => utility [patent_app_number] => 12/273979 [patent_app_country] => US [patent_app_date] => 2008-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 8558 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 490 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/751/07751252.pdf [firstpage_image] =>[orig_patent_app_number] => 12273979 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/273979
Semiconductor memory with a reference current generating circuit having a reference current generating section and an amplifier section Nov 18, 2008 Issued
Array ( [id] => 5269989 [patent_doc_number] => 20090073765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-19 [patent_title] => 'NON-VOLATILE MEMORY DEVICE AND METHOD HAVING BIT-STATE ASSIGNMENTS SELECTED TO MINIMIZE SIGNAL COUPLING' [patent_app_type] => utility [patent_app_number] => 12/272590 [patent_app_country] => US [patent_app_date] => 2008-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6267 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20090073765.pdf [firstpage_image] =>[orig_patent_app_number] => 12272590 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/272590
Non-volatile memory device and method having bit-state assignments selected to minimize signal coupling Nov 16, 2008 Issued
Array ( [id] => 5451203 [patent_doc_number] => 20090067239 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 12/267519 [patent_app_country] => US [patent_app_date] => 2008-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10219 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20090067239.pdf [firstpage_image] =>[orig_patent_app_number] => 12267519 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/267519
Flash memory array with a top gate line dynamically coupled to a word line Nov 6, 2008 Issued
Array ( [id] => 5366247 [patent_doc_number] => 20090303806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-10 [patent_title] => 'SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/261851 [patent_app_country] => US [patent_app_date] => 2008-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9972 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0303/20090303806.pdf [firstpage_image] =>[orig_patent_app_number] => 12261851 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/261851
SYNCHRONOUS SEMICONDUCTOR MEMORY DEVICE Oct 29, 2008 Abandoned
Array ( [id] => 6309947 [patent_doc_number] => 20100110745 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-06 [patent_title] => 'SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 12/261963 [patent_app_country] => US [patent_app_date] => 2008-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7496 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20100110745.pdf [firstpage_image] =>[orig_patent_app_number] => 12261963 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/261963
Switched interface stacked-die memory architecture Oct 29, 2008 Issued
Menu