| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 14221227
[patent_doc_number] => 20190122998
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-04-25
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/112824
[patent_app_country] => US
[patent_app_date] => 2018-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8417
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16112824
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/112824 | Semiconductor device with high quality and reliability wiring connection, and method for manufacturing the same | Aug 26, 2018 | Issued |
Array
(
[id] => 14382071
[patent_doc_number] => 20190164948
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-05-30
[patent_title] => PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/112785
[patent_app_country] => US
[patent_app_date] => 2018-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4170
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16112785
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/112785 | PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF | Aug 26, 2018 | Abandoned |
Array
(
[id] => 15611485
[patent_doc_number] => 10586813
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-10
[patent_title] => Array substrate with hollow display region, primary and second data lines and auxiliary data lines, and display panel and display device thereof
[patent_app_type] => utility
[patent_app_number] => 16/112792
[patent_app_country] => US
[patent_app_date] => 2018-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5402
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 166
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16112792
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/112792 | Array substrate with hollow display region, primary and second data lines and auxiliary data lines, and display panel and display device thereof | Aug 26, 2018 | Issued |
Array
(
[id] => 15733411
[patent_doc_number] => 10615140
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-04-07
[patent_title] => Semiconductor device suppressing an inclination of a semiconductor element after solder bonding
[patent_app_type] => utility
[patent_app_number] => 16/112818
[patent_app_country] => US
[patent_app_date] => 2018-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2607
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16112818
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/112818 | Semiconductor device suppressing an inclination of a semiconductor element after solder bonding | Aug 26, 2018 | Issued |
Array
(
[id] => 13754463
[patent_doc_number] => 10170183
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2019-01-01
[patent_title] => Method of storing and retrieving data for a resistive random access memory (RRAM) array with multi-memory cells per bit
[patent_app_type] => utility
[patent_app_number] => 16/102959
[patent_app_country] => US
[patent_app_date] => 2018-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3469
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16102959
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/102959 | Method of storing and retrieving data for a resistive random access memory (RRAM) array with multi-memory cells per bit | Aug 13, 2018 | Issued |
Array
(
[id] => 13740777
[patent_doc_number] => 20180374858
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-27
[patent_title] => Method of manufacturing a static random access memory (SRAM) using FinFETs with varying widths of fin structures
[patent_app_type] => utility
[patent_app_number] => 16/102169
[patent_app_country] => US
[patent_app_date] => 2018-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6576
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16102169
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/102169 | Method of manufacturing a static random access memory (SRAM) using FinFETs with varying widths of fin structures | Aug 12, 2018 | Issued |
Array
(
[id] => 14205105
[patent_doc_number] => 10269674
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-23
[patent_title] => Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors
[patent_app_type] => utility
[patent_app_number] => 16/053133
[patent_app_country] => US
[patent_app_date] => 2018-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 46
[patent_figures_cnt] => 46
[patent_no_of_words] => 5857
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16053133
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/053133 | Method of manufacturing an integrated fan-out package having fan-out redistribution layer (RDL) to accommodate electrical connectors | Aug 1, 2018 | Issued |
Array
(
[id] => 14631741
[patent_doc_number] => 20190229242
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-07-25
[patent_title] => SEMICONDUCTOR LIGHT EMITTING DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/045951
[patent_app_country] => US
[patent_app_date] => 2018-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6113
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16045951
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/045951 | Semiconductor light emitting device with increased reflectance and light emission efficiency, and suppressed peeling or migration of the reflective metal | Jul 25, 2018 | Issued |
Array
(
[id] => 15889895
[patent_doc_number] => 10651305
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-05-12
[patent_title] => Compound semiconductor device with quantum well structure, power supply device, and high-frequency amplifier
[patent_app_type] => utility
[patent_app_number] => 16/045960
[patent_app_country] => US
[patent_app_date] => 2018-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 40
[patent_no_of_words] => 9880
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16045960
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/045960 | Compound semiconductor device with quantum well structure, power supply device, and high-frequency amplifier | Jul 25, 2018 | Issued |
Array
(
[id] => 16881273
[patent_doc_number] => 11031430
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-08
[patent_title] => Image sensor with dummy lines for minimizing fixed pattern noise (FPN) and electronic apparatus including the same
[patent_app_type] => utility
[patent_app_number] => 16/045985
[patent_app_country] => US
[patent_app_date] => 2018-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 27
[patent_no_of_words] => 11074
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16045985
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/045985 | Image sensor with dummy lines for minimizing fixed pattern noise (FPN) and electronic apparatus including the same | Jul 25, 2018 | Issued |
Array
(
[id] => 13527851
[patent_doc_number] => 20180315468
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-01
[patent_title] => MULTI CHANNEL SEMICONDUCTOR DEVICE HAVING MULTI DIES AND OPERATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/032837
[patent_app_country] => US
[patent_app_date] => 2018-07-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11369
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16032837
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/032837 | Multi channel semiconductor device having multi dies and operation method thereof | Jul 10, 2018 | Issued |
Array
(
[id] => 15351659
[patent_doc_number] => 20200013721
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-09
[patent_title] => SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/030826
[patent_app_country] => US
[patent_app_date] => 2018-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4561
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030826
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/030826 | Semiconductor package with a conductive casing for heat dissipation and electromagnetic interference (EMI) shield and manufacturing method thereof | Jul 8, 2018 | Issued |
Array
(
[id] => 13613123
[patent_doc_number] => 20180358111
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-12-13
[patent_title] => SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE
[patent_app_type] => utility
[patent_app_number] => 16/026833
[patent_app_country] => US
[patent_app_date] => 2018-07-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7356
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16026833
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/026833 | Switched interface stacked-die memory architecture | Jul 2, 2018 | Issued |
Array
(
[id] => 13514523
[patent_doc_number] => 20180308804
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-10-25
[patent_title] => DEVICE HAVING SUBSTRATE WITH CONDUCTIVE PILLARS
[patent_app_type] => utility
[patent_app_number] => 16/025338
[patent_app_country] => US
[patent_app_date] => 2018-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3849
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 103
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16025338
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/025338 | Device having substrate with conductive pillars | Jul 1, 2018 | Issued |
Array
(
[id] => 15218153
[patent_doc_number] => 20190371763
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-05
[patent_title] => DIE STACKING FOR MULTI-TIER 3D INTEGRATION
[patent_app_type] => utility
[patent_app_number] => 15/991573
[patent_app_country] => US
[patent_app_date] => 2018-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5229
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15991573
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/991573 | Die stacking for multi-tier 3D integration | May 28, 2018 | Issued |
Array
(
[id] => 13570999
[patent_doc_number] => 20180337047
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-22
[patent_title] => METHODS OF ETCHING HARDMASKS CONTAINING HIGH HARDNESS MATERIALS
[patent_app_type] => utility
[patent_app_number] => 15/984285
[patent_app_country] => US
[patent_app_date] => 2018-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5120
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15984285
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/984285 | Method of etching hardmasks containing high hardness materials | May 17, 2018 | Issued |
Array
(
[id] => 15148599
[patent_doc_number] => 20190352777
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-11-21
[patent_title] => SHOWERHEAD WITH AIR-GAPPED PLENUMS AND OVERHEAD ISOLATION GAS DISTRIBUTOR
[patent_app_type] => utility
[patent_app_number] => 15/982913
[patent_app_country] => US
[patent_app_date] => 2018-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7660
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 284
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15982913
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/982913 | Showerhead with air-gapped plenums and overhead isolation gas distributor | May 16, 2018 | Issued |
Array
(
[id] => 13541373
[patent_doc_number] => 20180322233
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-11-08
[patent_title] => INTEGRATED CIRCUITS INCLUDING CELLS ARRANGED CONSIDERING SUPPLY VOLTAGE VARIATION OF CELLS AND INFLUENCE BETWEEN CELLS AND DESIGN METHODS THEREOF
[patent_app_type] => utility
[patent_app_number] => 15/968979
[patent_app_country] => US
[patent_app_date] => 2018-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13929
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15968979
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/968979 | Integrated circuit including cells/gates arranged based on supply voltage variations of cells and influence between cells, and design method thereof | May 1, 2018 | Issued |
Array
(
[id] => 14722521
[patent_doc_number] => 20190252324
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-08-15
[patent_title] => HERMETIC FLAT TOP INTEGRATED HEAT SPREADER ( IHS)/ELECTROMAGNETIC INTERFERENCE (EMI) SHIELD PACKAGE AND METHOD OF MANUFACTURING THEREOF FOR REDUCING WARPAGE
[patent_app_type] => utility
[patent_app_number] => 15/957831
[patent_app_country] => US
[patent_app_date] => 2018-04-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5828
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15957831
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/957831 | Hermetic flat top integrated heat spreader (IHS)/electromagnetic interference (EMI) shield package and method of manufacturing thereof for reducing warpage | Apr 18, 2018 | Issued |
Array
(
[id] => 13349923
[patent_doc_number] => 20180226501
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-08-09
[patent_title] => SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 15/944345
[patent_app_country] => US
[patent_app_date] => 2018-04-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5772
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -26
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15944345
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/944345 | High-electron-mobility transistor (HEMT) structure capable of protecting a III-V compound layer and manufacturing method thereof | Apr 2, 2018 | Issued |