Search

Andrew Q. Tran

Examiner (ID: 7081)

Most Active Art Unit
2824
Art Unit(s)
2511, 2812, 2818, 2824, 2825, 2827
Total Applications
1878
Issued Applications
1746
Pending Applications
27
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12395604 [patent_doc_number] => 09966120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-05-08 [patent_title] => Semiconductor memory with a data sensing circuit equipped with a line level control block for precharging local I/O lines to a first and second power supply voltage in a read operation [patent_app_type] => utility [patent_app_number] => 15/391392 [patent_app_country] => US [patent_app_date] => 2016-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4837 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15391392 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/391392
Semiconductor memory with a data sensing circuit equipped with a line level control block for precharging local I/O lines to a first and second power supply voltage in a read operation Dec 26, 2016 Issued
Array ( [id] => 11840187 [patent_doc_number] => 20170221907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/340025 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7000 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340025 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340025
Static random access memory (SRAM) using FinFETs with varying widths of fin structures Oct 31, 2016 Issued
Array ( [id] => 12202340 [patent_doc_number] => 09905412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-27 [patent_title] => 'Method and solution for cleaning InGaAs (or III-V) substrates' [patent_app_type] => utility [patent_app_number] => 15/340292 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3459 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340292 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340292
Method and solution for cleaning InGaAs (or III-V) substrates Oct 31, 2016 Issued
Array ( [id] => 11623160 [patent_doc_number] => 20170133347 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'METHOD FOR MANUFACTURING SUBSTRATES' [patent_app_type] => utility [patent_app_number] => 15/340377 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6637 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340377 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340377
Method for direct bonding of III-V semiconductor substrates with a radical oxide layer Oct 31, 2016 Issued
Array ( [id] => 11666074 [patent_doc_number] => 20170154793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'CHIP PACKAGE METHOD AND CHIP PACKAGE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 15/340518 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2620 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340518 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340518
Chip package method for reducing chip leakage current Oct 31, 2016 Issued
Array ( [id] => 12168327 [patent_doc_number] => 09887099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-06 [patent_title] => 'Pattern forming method capable of minimizing deviation of an inversion pattern' [patent_app_type] => utility [patent_app_number] => 15/340508 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 9279 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340508 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340508
Pattern forming method capable of minimizing deviation of an inversion pattern Oct 31, 2016 Issued
Array ( [id] => 12692836 [patent_doc_number] => 20180122778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => INTEGRATED CIRCUIT MODULE AND METHOD OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 15/340458 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8057 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340458 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340458
Integrated circuit module and method of forming same Oct 31, 2016 Issued
Array ( [id] => 14333431 [patent_doc_number] => 10297745 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-21 [patent_title] => Composite spacer layer for magnetoresistive memory [patent_app_type] => utility [patent_app_number] => 15/339928 [patent_app_country] => US [patent_app_date] => 2016-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10434 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15339928 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/339928
Composite spacer layer for magnetoresistive memory Oct 30, 2016 Issued
Array ( [id] => 15611641 [patent_doc_number] => 10586892 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-10 [patent_title] => Light emitting device with an electrostatic discharge (ESD) suppression pattern having first and second conductive particles dispersed in a resin [patent_app_type] => utility [patent_app_number] => 15/770158 [patent_app_country] => US [patent_app_date] => 2016-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 6302 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15770158 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/770158
Light emitting device with an electrostatic discharge (ESD) suppression pattern having first and second conductive particles dispersed in a resin Oct 20, 2016 Issued
Array ( [id] => 13528391 [patent_doc_number] => 20180315738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => MICROELECTRONIC DIODE WITH OPTIMISED ACTIVE SURFACE [patent_app_type] => utility [patent_app_number] => 15/769962 [patent_app_country] => US [patent_app_date] => 2016-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15769962 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/769962
Microelectronic diode with optimised active surface Oct 19, 2016 Issued
Array ( [id] => 14268207 [patent_doc_number] => 10283676 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Light-emitting diode chip with one of a mirror layer and an adhesion-promoting layer for high efficiency and long service life [patent_app_type] => utility [patent_app_number] => 15/769996 [patent_app_country] => US [patent_app_date] => 2016-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 8821 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15769996 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/769996
Light-emitting diode chip with one of a mirror layer and an adhesion-promoting layer for high efficiency and long service life Oct 18, 2016 Issued
Array ( [id] => 11592048 [patent_doc_number] => 20170116458 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'SENSING DEVICE AND METHOD FOR FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/297546 [patent_app_country] => US [patent_app_date] => 2016-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6049 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15297546 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/297546
Wafer-level packaging sensing device and method for forming the same Oct 18, 2016 Issued
Array ( [id] => 11608030 [patent_doc_number] => 20170125333 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-04 [patent_title] => 'WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/297782 [patent_app_country] => US [patent_app_date] => 2016-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11758 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15297782 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/297782
Careless wiring substrate having an insulation layer with a bulged covering portion and semiconductor device thereof Oct 18, 2016 Issued
Array ( [id] => 12650751 [patent_doc_number] => 20180108748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => Gate Structure and Method of Forming the Same [patent_app_type] => utility [patent_app_number] => 15/297850 [patent_app_country] => US [patent_app_date] => 2016-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9829 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15297850 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/297850
Method of forming a FinFET with work function tuning layers having stair-step increment sidewalls Oct 18, 2016 Issued
Array ( [id] => 12168422 [patent_doc_number] => 09887195 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-02-06 [patent_title] => 'Coaxial connector feed-through for multi-level interconnected semiconductor wafers' [patent_app_type] => utility [patent_app_number] => 15/297803 [patent_app_country] => US [patent_app_date] => 2016-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 3408 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15297803 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/297803
Coaxial connector feed-through for multi-level interconnected semiconductor wafers Oct 18, 2016 Issued
Array ( [id] => 12650355 [patent_doc_number] => 20180108616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-04-19 [patent_title] => DEVICE HAVING SUBSTRATE WITH CONDUCTIVE PILLARS [patent_app_type] => utility [patent_app_number] => 15/297744 [patent_app_country] => US [patent_app_date] => 2016-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3822 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15297744 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/297744
Device having substrate with conductive pillars Oct 18, 2016 Issued
Array ( [id] => 16881230 [patent_doc_number] => 11031387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => PN diodes and connected group III-N devices and their methods of fabrication [patent_app_type] => utility [patent_app_number] => 16/322082 [patent_app_country] => US [patent_app_date] => 2016-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 14392 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16322082 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/322082
PN diodes and connected group III-N devices and their methods of fabrication Sep 29, 2016 Issued
Array ( [id] => 12257015 [patent_doc_number] => 09929165 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-03-27 [patent_title] => 'Method for producing integrated circuit memory cells with less dedicated lithographic steps' [patent_app_type] => utility [patent_app_number] => 15/278112 [patent_app_country] => US [patent_app_date] => 2016-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 5451 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15278112 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/278112
Method for producing integrated circuit memory cells with less dedicated lithographic steps Sep 27, 2016 Issued
Array ( [id] => 12498225 [patent_doc_number] => 09997369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-12 [patent_title] => Margin for fin cut using self-aligned triple patterning [patent_app_type] => utility [patent_app_number] => 15/277431 [patent_app_country] => US [patent_app_date] => 2016-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 6427 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15277431 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/277431
Margin for fin cut using self-aligned triple patterning Sep 26, 2016 Issued
Array ( [id] => 12969076 [patent_doc_number] => 09875932 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-23 [patent_title] => Methods of forming contact holes using pillar masks and mask bridges [patent_app_type] => utility [patent_app_number] => 15/277636 [patent_app_country] => US [patent_app_date] => 2016-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 43 [patent_no_of_words] => 11504 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15277636 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/277636
Methods of forming contact holes using pillar masks and mask bridges Sep 26, 2016 Issued
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