Andrew Q. Tran

Array ( [id] => 11439454 [patent_doc_number] => 20170040475 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-02-09 [patent_title] => 'AROMATIC POLYIMIDE FILM, LAMINATE, AND SOLAR CELL' [patent_app_type] => utility [patent_app_number] => 15/274762 [patent_app_country] => US [patent_app_date] => 2016-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 13088 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15274762 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11366903 [patent_doc_number] => 20170004884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-01-05 [patent_title] => 'WRITING MULTIPLE LEVELS IN A PHASE CHANGE MEMORY' [patent_app_type] => utility [patent_app_number] => 15/266186 [patent_app_country] => US [patent_app_date] => 2016-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 14580 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15266186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13681595 [patent_doc_number] => 20160379534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => DRIVING METHOD OF LIQUID CRYSTAL DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 15/259360 [patent_app_country] => US [patent_app_date] => 2016-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17029 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15259360 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11350371 [patent_doc_number] => 20160369112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'MIXTURES, METHODS AND COMPOSITIONS PERTAINING TO CONDUCTIVE MATERIALS' [patent_app_type] => utility [patent_app_number] => 15/234310 [patent_app_country] => US [patent_app_date] => 2016-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 12012 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15234310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11273508 [patent_doc_number] => 20160336056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'Dram-Type Device With Low Variation Transistor Peripheral Circuits, and Related Methods' [patent_app_type] => utility [patent_app_number] => 15/218757 [patent_app_country] => US [patent_app_date] => 2016-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 17687 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15218757 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12918556 [patent_doc_number] => 20180198028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-12 [patent_title] => OPTOELECTRONIC SEMICONDUCTOR CHIP [patent_app_type] => utility [patent_app_number] => 15/741860 [patent_app_country] => US [patent_app_date] => 2016-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5395 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15741860 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14616563 [patent_doc_number] => 10360985 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Method and apparatus for staggered start-up of a predefined, random, or dynamic number of flash memory devices [patent_app_type] => utility [patent_app_number] => 15/198235 [patent_app_country] => US [patent_app_date] => 2016-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5179 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15198235 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11339754 [patent_doc_number] => 20160365510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-15 [patent_title] => 'DUAL MODE MEMORY CELL APPARATUS AND METHODS' [patent_app_type] => utility [patent_app_number] => 15/189114 [patent_app_country] => US [patent_app_date] => 2016-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9271 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15189114 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11087796 [patent_doc_number] => 20160284764 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-29 [patent_title] => 'Method Of Manufacturing Semiconductor Device And Semiconductor Device Having Unequal Pitch Vertical Channel Transistors' [patent_app_type] => utility [patent_app_number] => 15/180559 [patent_app_country] => US [patent_app_date] => 2016-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 17969 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15180559 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11353453 [patent_doc_number] => 20160372193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'INTEGRATED SETBACK READ WITH REDUCED SNAPBACK DISTURB' [patent_app_type] => utility [patent_app_number] => 15/180556 [patent_app_country] => US [patent_app_date] => 2016-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8056 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15180556 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11831484 [patent_doc_number] => 09728232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-08 [patent_title] => 'System and method for automatic detection of power up for a dual-rail circuit' [patent_app_type] => utility [patent_app_number] => 15/167101 [patent_app_country] => US [patent_app_date] => 2016-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 5885 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15167101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11063541 [patent_doc_number] => 20160260503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-08 [patent_title] => 'SWITCHED INTERFACE STACKED-DIE MEMORY ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 15/155848 [patent_app_country] => US [patent_app_date] => 2016-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7581 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15155848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14267769 [patent_doc_number] => 10283456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Lithography engraving machine for forming water identification marks and aligment marks [patent_app_type] => utility [patent_app_number] => 15/154181 [patent_app_country] => US [patent_app_date] => 2016-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 5545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15154181 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13682465 [patent_doc_number] => 20160379969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-29 [patent_title] => Patterned Wafer and Method of Making the Same [patent_app_type] => utility [patent_app_number] => 15/152885 [patent_app_country] => US [patent_app_date] => 2016-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2862 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15152885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13005889 [patent_doc_number] => 10026615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => Fin patterns with varying spacing without Fin cut [patent_app_type] => utility [patent_app_number] => 15/153226 [patent_app_country] => US [patent_app_date] => 2016-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3701 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15153226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11273841 [patent_doc_number] => 20160336388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-11-17 [patent_title] => 'METHOD FOR FORMING Ti/TiN STACKED FILM AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/153205 [patent_app_country] => US [patent_app_date] => 2016-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5501 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15153205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11517502 [patent_doc_number] => 20170084576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-23 [patent_title] => 'Integrated Fan-out Stacked SiP and the Methods of Manufacturing' [patent_app_type] => utility [patent_app_number] => 15/130211 [patent_app_country] => US [patent_app_date] => 2016-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 63 [patent_figures_cnt] => 63 [patent_no_of_words] => 10821 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15130211 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11847617 [patent_doc_number] => 09735173 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-08-15 [patent_title] => 'Reduced parasitic capacitance and contact resistance in extremely thin silicon-on-insulator (ETSOI) devices due to wrap-around structure of source/drain regions' [patent_app_type] => utility [patent_app_number] => 15/072920 [patent_app_country] => US [patent_app_date] => 2016-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4985 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15072920 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12315036 [patent_doc_number] => 09941398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-10 [patent_title] => High-electron-mobility transistor (HEMT) capable of protecting a III-V compound layer [patent_app_type] => utility [patent_app_number] => 15/072992 [patent_app_country] => US [patent_app_date] => 2016-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5490 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15072992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13201727 [patent_doc_number] => 10115784 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-30 [patent_title] => Semiconductor device, MIM capacitor and associated fabricating method [patent_app_type] => utility [patent_app_number] => 15/072951 [patent_app_country] => US [patent_app_date] => 2016-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5199 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15072951 [rel_patent_id] =>[rel_patent_doc_number] =>)