
Andrew Sanders
Examiner (ID: 3675)
| Most Active Art Unit | 2509 |
| Art Unit(s) | 2504, 2509 |
| Total Applications | 463 |
| Issued Applications | 431 |
| Pending Applications | 2 |
| Abandoned Applications | 30 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3555801
[patent_doc_number] => 05572149
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-05
[patent_title] => 'Clock regeneration circuit'
[patent_app_type] => 1
[patent_app_number] => 8/584945
[patent_app_country] => US
[patent_app_date] => 1996-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 16
[patent_no_of_words] => 3279
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/572/05572149.pdf
[firstpage_image] =>[orig_patent_app_number] => 584945
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/584945 | Clock regeneration circuit | Jan 15, 1996 | Issued |
Array
(
[id] => 3555851
[patent_doc_number] => 05572152
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-05
[patent_title] => 'Logic circuit with the function of controlling discharge current on pull-down and emitter coupled logic circuit'
[patent_app_type] => 1
[patent_app_number] => 8/573604
[patent_app_country] => US
[patent_app_date] => 1995-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4728
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 197
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/572/05572152.pdf
[firstpage_image] =>[orig_patent_app_number] => 573604
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/573604 | Logic circuit with the function of controlling discharge current on pull-down and emitter coupled logic circuit | Dec 14, 1995 | Issued |
Array
(
[id] => 3535698
[patent_doc_number] => 05583454
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-10
[patent_title] => 'Programmable input/output driver circuit capable of operating at a variety of voltage levels and having a programmable pullup/pulldown function'
[patent_app_type] => 1
[patent_app_number] => 8/566131
[patent_app_country] => US
[patent_app_date] => 1995-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 8507
[patent_no_of_claims] => 34
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[patent_words_short_claim] => 132
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/583/05583454.pdf
[firstpage_image] =>[orig_patent_app_number] => 566131
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/566131 | Programmable input/output driver circuit capable of operating at a variety of voltage levels and having a programmable pullup/pulldown function | Nov 30, 1995 | Issued |
Array
(
[id] => 3669830
[patent_doc_number] => 05598105
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-28
[patent_title] => 'Elementary cell for constructing asynchronous superconducting logic circuits'
[patent_app_type] => 1
[patent_app_number] => 8/562746
[patent_app_country] => US
[patent_app_date] => 1995-11-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 11
[patent_no_of_words] => 9199
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/598/05598105.pdf
[firstpage_image] =>[orig_patent_app_number] => 562746
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/562746 | Elementary cell for constructing asynchronous superconducting logic circuits | Nov 26, 1995 | Issued |
Array
(
[id] => 3532040
[patent_doc_number] => 05541527
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'PECL buffer'
[patent_app_type] => 1
[patent_app_number] => 8/551127
[patent_app_country] => US
[patent_app_date] => 1995-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2539
[patent_no_of_claims] => 18
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[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/541/05541527.pdf
[firstpage_image] =>[orig_patent_app_number] => 551127
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/551127 | PECL buffer | Oct 30, 1995 | Issued |
Array
(
[id] => 3530688
[patent_doc_number] => 05528175
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-18
[patent_title] => 'Devices for implementing microwave phase logic'
[patent_app_type] => 1
[patent_app_number] => 8/546634
[patent_app_country] => US
[patent_app_date] => 1995-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 8348
[patent_no_of_claims] => 15
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/528/05528175.pdf
[firstpage_image] =>[orig_patent_app_number] => 546634
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/546634 | Devices for implementing microwave phase logic | Oct 29, 1995 | Issued |
Array
(
[id] => 3608062
[patent_doc_number] => 05578944
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-26
[patent_title] => 'Signal receiver and apparatus incorporating same'
[patent_app_type] => 1
[patent_app_number] => 8/542492
[patent_app_country] => US
[patent_app_date] => 1995-10-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2317
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/578/05578944.pdf
[firstpage_image] =>[orig_patent_app_number] => 542492
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/542492 | Signal receiver and apparatus incorporating same | Oct 12, 1995 | Issued |
Array
(
[id] => 3521207
[patent_doc_number] => 05576643
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-19
[patent_title] => 'Data transfer circuit device'
[patent_app_type] => 1
[patent_app_number] => 8/540626
[patent_app_country] => US
[patent_app_date] => 1995-10-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3626
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/576/05576643.pdf
[firstpage_image] =>[orig_patent_app_number] => 540626
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/540626 | Data transfer circuit device | Oct 5, 1995 | Issued |
Array
(
[id] => 3593493
[patent_doc_number] => 05550491
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-27
[patent_title] => 'Current-mode logic circuit'
[patent_app_type] => 1
[patent_app_number] => 8/531931
[patent_app_country] => US
[patent_app_date] => 1995-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3163
[patent_no_of_claims] => 4
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[patent_words_short_claim] => 205
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/550/05550491.pdf
[firstpage_image] =>[orig_patent_app_number] => 531931
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/531931 | Current-mode logic circuit | Sep 20, 1995 | Issued |
Array
(
[id] => 3535724
[patent_doc_number] => 05583456
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-10
[patent_title] => 'Differentially coupled AND/NAND and XOR/XNOR circuitry'
[patent_app_type] => 1
[patent_app_number] => 8/519172
[patent_app_country] => US
[patent_app_date] => 1995-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 14
[patent_no_of_words] => 3150
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/583/05583456.pdf
[firstpage_image] =>[orig_patent_app_number] => 519172
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/519172 | Differentially coupled AND/NAND and XOR/XNOR circuitry | Aug 24, 1995 | Issued |
Array
(
[id] => 3532054
[patent_doc_number] => 05541528
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'CMOS buffer circuit having increased speed'
[patent_app_type] => 1
[patent_app_number] => 8/519443
[patent_app_country] => US
[patent_app_date] => 1995-08-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 4376
[patent_no_of_claims] => 27
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/541/05541528.pdf
[firstpage_image] =>[orig_patent_app_number] => 519443
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/519443 | CMOS buffer circuit having increased speed | Aug 24, 1995 | Issued |
Array
(
[id] => 3512428
[patent_doc_number] => 05570036
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-29
[patent_title] => 'CMOS buffer circuit having power-down feature'
[patent_app_type] => 1
[patent_app_number] => 8/519444
[patent_app_country] => US
[patent_app_date] => 1995-08-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/570/05570036.pdf
[firstpage_image] =>[orig_patent_app_number] => 519444
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/519444 | CMOS buffer circuit having power-down feature | Aug 24, 1995 | Issued |
Array
(
[id] => 3596082
[patent_doc_number] => 05568070
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-22
[patent_title] => 'Multiplexer w/ selective switching for external signals'
[patent_app_type] => 1
[patent_app_number] => 8/519335
[patent_app_country] => US
[patent_app_date] => 1995-08-25
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[pdf_file] => patents/05/568/05568070.pdf
[firstpage_image] =>[orig_patent_app_number] => 519335
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/519335 | Multiplexer w/ selective switching for external signals | Aug 24, 1995 | Issued |
Array
(
[id] => 3617870
[patent_doc_number] => 05565798
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'Self-timed control circuit for self-resetting logic circuitry'
[patent_app_type] => 1
[patent_app_number] => 8/517224
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[patent_app_date] => 1995-08-21
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[pdf_file] => patents/05/565/05565798.pdf
[firstpage_image] =>[orig_patent_app_number] => 517224
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/517224 | Self-timed control circuit for self-resetting logic circuitry | Aug 20, 1995 | Issued |
Array
(
[id] => 3617750
[patent_doc_number] => 05534789
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-09
[patent_title] => 'Mixed mode output buffer circuit for CMOSIC'
[patent_app_type] => 1
[patent_app_number] => 8/512237
[patent_app_country] => US
[patent_app_date] => 1995-08-07
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[pdf_file] => patents/05/534/05534789.pdf
[firstpage_image] =>[orig_patent_app_number] => 512237
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/512237 | Mixed mode output buffer circuit for CMOSIC | Aug 6, 1995 | Issued |
Array
(
[id] => 3593948
[patent_doc_number] => 05517135
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-14
[patent_title] => 'Bidirectional tristate buffer with default input'
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[pdf_file] => patents/05/517/05517135.pdf
[firstpage_image] =>[orig_patent_app_number] => 507626
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/507626 | Bidirectional tristate buffer with default input | Jul 25, 1995 | Issued |
Array
(
[id] => 3501867
[patent_doc_number] => 05561694
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-01
[patent_title] => 'Self-timed driver circuit'
[patent_app_type] => 1
[patent_app_number] => 8/506933
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[pdf_file] => patents/05/561/05561694.pdf
[firstpage_image] =>[orig_patent_app_number] => 506933
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/506933 | Self-timed driver circuit | Jul 25, 1995 | Issued |
Array
(
[id] => 3664504
[patent_doc_number] => 05592108
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-07
[patent_title] => 'Interface circuit adapted for connection to following circuit using metal-semiconductor type transistor'
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[patent_app_number] => 8/506638
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[pdf_file] => patents/05/592/05592108.pdf
[firstpage_image] =>[orig_patent_app_number] => 506638
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/506638 | Interface circuit adapted for connection to following circuit using metal-semiconductor type transistor | Jul 24, 1995 | Issued |
Array
(
[id] => 3617826
[patent_doc_number] => 05565795
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'Level converting circuit for reducing an on-quiescence current'
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[pdf_file] => patents/05/565/05565795.pdf
[firstpage_image] =>[orig_patent_app_number] => 504734
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/504734 | Level converting circuit for reducing an on-quiescence current | Jul 18, 1995 | Issued |
Array
(
[id] => 3595967
[patent_doc_number] => 05568062
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-22
[patent_title] => 'Low noise tri-state output buffer'
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/568/05568062.pdf
[firstpage_image] =>[orig_patent_app_number] => 502531
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/502531 | Low noise tri-state output buffer | Jul 13, 1995 | Issued |