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Andrew Sanders

Examiner (ID: 3675)

Most Active Art Unit
2509
Art Unit(s)
2504, 2509
Total Applications
463
Issued Applications
431
Pending Applications
2
Abandoned Applications
30

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3069235 [patent_doc_number] => 05311083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-10 [patent_title] => 'Very low voltage inter-chip CMOS logic signaling for large numbers of high-speed output lines each associated with large capacitive loads' [patent_app_type] => 1 [patent_app_number] => 8/008669 [patent_app_country] => US [patent_app_date] => 1993-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4751 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/311/05311083.pdf [firstpage_image] =>[orig_patent_app_number] => 008669 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/008669
Very low voltage inter-chip CMOS logic signaling for large numbers of high-speed output lines each associated with large capacitive loads Jan 24, 1993 Issued
Array ( [id] => 3003187 [patent_doc_number] => 05359240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-25 [patent_title] => 'Low power digital signal buffer circuit' [patent_app_type] => 1 [patent_app_number] => 8/008165 [patent_app_country] => US [patent_app_date] => 1993-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2528 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/359/05359240.pdf [firstpage_image] =>[orig_patent_app_number] => 008165 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/008165
Low power digital signal buffer circuit Jan 24, 1993 Issued
Array ( [id] => 3075760 [patent_doc_number] => 05361003 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-01 [patent_title] => 'Adjustable buffer driver' [patent_app_type] => 1 [patent_app_number] => 8/004363 [patent_app_country] => US [patent_app_date] => 1993-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 2522 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/361/05361003.pdf [firstpage_image] =>[orig_patent_app_number] => 004363 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/004363
Adjustable buffer driver Jan 13, 1993 Issued
Array ( [id] => 2995476 [patent_doc_number] => 05347177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-13 [patent_title] => 'System for interconnecting VLSI circuits with transmission line characteristics' [patent_app_type] => 1 [patent_app_number] => 8/004364 [patent_app_country] => US [patent_app_date] => 1993-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7512 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/347/05347177.pdf [firstpage_image] =>[orig_patent_app_number] => 004364 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/004364
System for interconnecting VLSI circuits with transmission line characteristics Jan 13, 1993 Issued
Array ( [id] => 3033610 [patent_doc_number] => 05349246 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-20 [patent_title] => 'Input buffer with hysteresis characteristics' [patent_app_type] => 1 [patent_app_number] => 7/995666 [patent_app_country] => US [patent_app_date] => 1992-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3853 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/349/05349246.pdf [firstpage_image] =>[orig_patent_app_number] => 995666 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/995666
Input buffer with hysteresis characteristics Dec 20, 1992 Issued
Array ( [id] => 3003167 [patent_doc_number] => 05359239 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-25 [patent_title] => 'Output circuit with reduced switching noise' [patent_app_type] => 1 [patent_app_number] => 7/993065 [patent_app_country] => US [patent_app_date] => 1992-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 4834 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/359/05359239.pdf [firstpage_image] =>[orig_patent_app_number] => 993065 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/993065
Output circuit with reduced switching noise Dec 17, 1992 Issued
Array ( [id] => 3418075 [patent_doc_number] => 05444393 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-22 [patent_title] => 'Semiconductor integrated circuit for selectively performing a rewiring or a logical operation' [patent_app_type] => 1 [patent_app_number] => 7/992762 [patent_app_country] => US [patent_app_date] => 1992-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 24 [patent_no_of_words] => 7951 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/444/05444393.pdf [firstpage_image] =>[orig_patent_app_number] => 992762 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/992762
Semiconductor integrated circuit for selectively performing a rewiring or a logical operation Dec 17, 1992 Issued
Array ( [id] => 3000198 [patent_doc_number] => 05362997 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-08 [patent_title] => 'BiCMOS output driver' [patent_app_type] => 1 [patent_app_number] => 7/991568 [patent_app_country] => US [patent_app_date] => 1992-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4304 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/362/05362997.pdf [firstpage_image] =>[orig_patent_app_number] => 991568 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/991568
BiCMOS output driver Dec 15, 1992 Issued
Array ( [id] => 3076261 [patent_doc_number] => 05336948 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-09 [patent_title] => 'Active negation emulator' [patent_app_type] => 1 [patent_app_number] => 7/991168 [patent_app_country] => US [patent_app_date] => 1992-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4876 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/336/05336948.pdf [firstpage_image] =>[orig_patent_app_number] => 991168 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/991168
Active negation emulator Dec 15, 1992 Issued
Array ( [id] => 3463976 [patent_doc_number] => 05382846 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-17 [patent_title] => 'Level shifting circuit for suppressing output amplitude' [patent_app_type] => 1 [patent_app_number] => 7/988971 [patent_app_country] => US [patent_app_date] => 1992-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 46 [patent_no_of_words] => 9158 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/382/05382846.pdf [firstpage_image] =>[orig_patent_app_number] => 988971 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/988971
Level shifting circuit for suppressing output amplitude Dec 9, 1992 Issued
07/986765 CIRCUIT FOR CALCULATING A MINIMUM VALUE Dec 7, 1992 Abandoned
07/986767 CIRCUIT FOR CALCULATING A MAXIMUM VALUE Dec 7, 1992 Abandoned
07/976717 APPARATUS AND METHOD FOR ECL-LIKE SIGNAL TO CMOS SIGNAL CONVERSION Nov 15, 1992 Abandoned
Array ( [id] => 3111894 [patent_doc_number] => 05418473 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-23 [patent_title] => 'Single event upset immune logic family' [patent_app_type] => 1 [patent_app_number] => 7/967457 [patent_app_country] => US [patent_app_date] => 1992-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6199 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/418/05418473.pdf [firstpage_image] =>[orig_patent_app_number] => 967457 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/967457
Single event upset immune logic family Oct 27, 1992 Issued
Array ( [id] => 3596488 [patent_doc_number] => 05550691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-27 [patent_title] => 'Size-independent, rigid-disk, magnetic, digital-information storage system with localized read/write enhancements' [patent_app_type] => 1 [patent_app_number] => 7/966095 [patent_app_country] => US [patent_app_date] => 1992-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 6954 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/550/05550691.pdf [firstpage_image] =>[orig_patent_app_number] => 966095 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/966095
Size-independent, rigid-disk, magnetic, digital-information storage system with localized read/write enhancements Oct 21, 1992 Issued
Array ( [id] => 3012170 [patent_doc_number] => 05331219 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-19 [patent_title] => 'Semiconductor integrated circuit with selective interfacing on different interface levels' [patent_app_type] => 1 [patent_app_number] => 7/964864 [patent_app_country] => US [patent_app_date] => 1992-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2456 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/331/05331219.pdf [firstpage_image] =>[orig_patent_app_number] => 964864 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/964864
Semiconductor integrated circuit with selective interfacing on different interface levels Oct 21, 1992 Issued
Array ( [id] => 3463961 [patent_doc_number] => 05382845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-17 [patent_title] => 'ECL to CMOS level converter' [patent_app_type] => 1 [patent_app_number] => 7/961865 [patent_app_country] => US [patent_app_date] => 1992-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 8224 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/382/05382845.pdf [firstpage_image] =>[orig_patent_app_number] => 961865 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/961865
ECL to CMOS level converter Oct 14, 1992 Issued
07/958866 PROGRAMMABLE APPLICATION SPECIFIC INTEGRATED CIRCUIT AND LOGIC CELL THEREFOR Oct 7, 1992 Abandoned
Array ( [id] => 3015020 [patent_doc_number] => 05276366 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-04 [patent_title] => 'Digital voltage level translator circuit' [patent_app_type] => 1 [patent_app_number] => 7/955567 [patent_app_country] => US [patent_app_date] => 1992-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3543 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/276/05276366.pdf [firstpage_image] =>[orig_patent_app_number] => 955567 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/955567
Digital voltage level translator circuit Oct 1, 1992 Issued
Array ( [id] => 3098326 [patent_doc_number] => 05291077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-01 [patent_title] => 'Semiconductor logical FET device' [patent_app_type] => 1 [patent_app_number] => 7/955159 [patent_app_country] => US [patent_app_date] => 1992-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3402 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/291/05291077.pdf [firstpage_image] =>[orig_patent_app_number] => 955159 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/955159
Semiconductor logical FET device Sep 30, 1992 Issued
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