
Andrew Sanders
Examiner (ID: 1323)
| Most Active Art Unit | 2509 |
| Art Unit(s) | 2509, 2504 |
| Total Applications | 463 |
| Issued Applications | 431 |
| Pending Applications | 2 |
| Abandoned Applications | 30 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3033626
[patent_doc_number] => 05349247
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-20
[patent_title] => 'Enhancement circuit and method for ensuring diactuation of a switching device'
[patent_app_type] => 1
[patent_app_number] => 7/893880
[patent_app_country] => US
[patent_app_date] => 1992-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2260
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/349/05349247.pdf
[firstpage_image] =>[orig_patent_app_number] => 893880
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/893880 | Enhancement circuit and method for ensuring diactuation of a switching device | Jun 4, 1992 | Issued |
Array
(
[id] => 3032169
[patent_doc_number] => 05317205
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-31
[patent_title] => 'Semiconductor integrated circuit and associated test method'
[patent_app_type] => 1
[patent_app_number] => 7/892196
[patent_app_country] => US
[patent_app_date] => 1992-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2478
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 279
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/317/05317205.pdf
[firstpage_image] =>[orig_patent_app_number] => 892196
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/892196 | Semiconductor integrated circuit and associated test method | Jun 1, 1992 | Issued |
Array
(
[id] => 3025349
[patent_doc_number] => 05327022
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-05
[patent_title] => 'Multiplexer circuit less liable to malfunction'
[patent_app_type] => 1
[patent_app_number] => 7/885363
[patent_app_country] => US
[patent_app_date] => 1992-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5009
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/327/05327022.pdf
[firstpage_image] =>[orig_patent_app_number] => 885363
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/885363 | Multiplexer circuit less liable to malfunction | May 18, 1992 | Issued |
| 07/883076 | PROGRAMMABLE LOGIC DEVICE MACROCELL WITH AN EXCLUSIVE FEEDBACK LINE AND AN EXCLUSIVE EXTERNAL INPUT LINE | May 14, 1992 | Abandoned |
Array
(
[id] => 3041113
[patent_doc_number] => 05300830
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-05
[patent_title] => 'Programmable logic device macrocell with an exclusive feedback and exclusive external input lines for registered and combinatorial modes using a dedicated product term for control'
[patent_app_type] => 1
[patent_app_number] => 7/883078
[patent_app_country] => US
[patent_app_date] => 1992-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3626
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/300/05300830.pdf
[firstpage_image] =>[orig_patent_app_number] => 883078
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/883078 | Programmable logic device macrocell with an exclusive feedback and exclusive external input lines for registered and combinatorial modes using a dedicated product term for control | May 14, 1992 | Issued |
Array
(
[id] => 2968052
[patent_doc_number] => 05264746
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-23
[patent_title] => 'Logic circuit board with a clock observation circuit'
[patent_app_type] => 1
[patent_app_number] => 7/883383
[patent_app_country] => US
[patent_app_date] => 1992-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 3174
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/264/05264746.pdf
[firstpage_image] =>[orig_patent_app_number] => 883383
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/883383 | Logic circuit board with a clock observation circuit | May 14, 1992 | Issued |
Array
(
[id] => 3055369
[patent_doc_number] => 05306966
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-04-26
[patent_title] => 'High-speed and low-power consumption decoder unit implemented by emitter-coupled logic circuit'
[patent_app_type] => 1
[patent_app_number] => 7/883473
[patent_app_country] => US
[patent_app_date] => 1992-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 3762
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/306/05306966.pdf
[firstpage_image] =>[orig_patent_app_number] => 883473
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/883473 | High-speed and low-power consumption decoder unit implemented by emitter-coupled logic circuit | May 14, 1992 | Issued |
Array
(
[id] => 3032227
[patent_doc_number] => 05317208
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-31
[patent_title] => 'Integrated circuit employing inverse transistors'
[patent_app_type] => 1
[patent_app_number] => 7/881595
[patent_app_country] => US
[patent_app_date] => 1992-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 19
[patent_no_of_words] => 7796
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 146
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/317/05317208.pdf
[firstpage_image] =>[orig_patent_app_number] => 881595
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/881595 | Integrated circuit employing inverse transistors | May 11, 1992 | Issued |
Array
(
[id] => 3098216
[patent_doc_number] => 05291071
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-01
[patent_title] => 'High speed, low power output circuit with temperature compensated noise control'
[patent_app_type] => 1
[patent_app_number] => 7/881843
[patent_app_country] => US
[patent_app_date] => 1992-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2901
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 524
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/291/05291071.pdf
[firstpage_image] =>[orig_patent_app_number] => 881843
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/881843 | High speed, low power output circuit with temperature compensated noise control | May 11, 1992 | Issued |
Array
(
[id] => 2899814
[patent_doc_number] => 05241223
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-31
[patent_title] => 'NOR.sub.i circuit/bias generator combination compatible with CSEF circuits'
[patent_app_type] => 1
[patent_app_number] => 7/881592
[patent_app_country] => US
[patent_app_date] => 1992-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 4442
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/241/05241223.pdf
[firstpage_image] =>[orig_patent_app_number] => 881592
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/881592 | NOR.sub.i circuit/bias generator combination compatible with CSEF circuits | May 11, 1992 | Issued |
Array
(
[id] => 3070412
[patent_doc_number] => 05352939
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-04
[patent_title] => 'Master slice semiconductor integrated circuit with output drive current control'
[patent_app_type] => 1
[patent_app_number] => 7/838460
[patent_app_country] => US
[patent_app_date] => 1992-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4278
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 234
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/352/05352939.pdf
[firstpage_image] =>[orig_patent_app_number] => 838460
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/838460 | Master slice semiconductor integrated circuit with output drive current control | May 6, 1992 | Issued |
Array
(
[id] => 3034825
[patent_doc_number] => 05343092
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-30
[patent_title] => 'Self-biased feedback-controlled active pull-down signal switching'
[patent_app_type] => 1
[patent_app_number] => 7/874784
[patent_app_country] => US
[patent_app_date] => 1992-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 7
[patent_no_of_words] => 4108
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/343/05343092.pdf
[firstpage_image] =>[orig_patent_app_number] => 874784
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/874784 | Self-biased feedback-controlled active pull-down signal switching | Apr 26, 1992 | Issued |
Array
(
[id] => 2901781
[patent_doc_number] => 05245225
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-09-14
[patent_title] => 'High performance BiFET complementary emitter follower logic circuit'
[patent_app_type] => 1
[patent_app_number] => 7/874273
[patent_app_country] => US
[patent_app_date] => 1992-04-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 2461
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/245/05245225.pdf
[firstpage_image] =>[orig_patent_app_number] => 874273
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/874273 | High performance BiFET complementary emitter follower logic circuit | Apr 23, 1992 | Issued |
Array
(
[id] => 2924554
[patent_doc_number] => 05192882
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-09
[patent_title] => 'Synchronization circuit for parallel processing'
[patent_app_type] => 1
[patent_app_number] => 7/871584
[patent_app_country] => US
[patent_app_date] => 1992-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 26
[patent_no_of_words] => 9964
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 273
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/192/05192882.pdf
[firstpage_image] =>[orig_patent_app_number] => 871584
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/871584 | Synchronization circuit for parallel processing | Apr 19, 1992 | Issued |
Array
(
[id] => 3012347
[patent_doc_number] => 05331229
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-19
[patent_title] => 'CMOS/ECL signal level converter'
[patent_app_type] => 1
[patent_app_number] => 7/869472
[patent_app_country] => US
[patent_app_date] => 1992-04-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2810
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 310
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/331/05331229.pdf
[firstpage_image] =>[orig_patent_app_number] => 869472
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/869472 | CMOS/ECL signal level converter | Apr 14, 1992 | Issued |
Array
(
[id] => 3104449
[patent_doc_number] => 05315172
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-24
[patent_title] => 'Reduced noise output buffer'
[patent_app_type] => 1
[patent_app_number] => 7/868399
[patent_app_country] => US
[patent_app_date] => 1992-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1440
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 180
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/315/05315172.pdf
[firstpage_image] =>[orig_patent_app_number] => 868399
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/868399 | Reduced noise output buffer | Apr 13, 1992 | Issued |
Array
(
[id] => 3090823
[patent_doc_number] => 05285119
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-02-08
[patent_title] => 'Semiconductor integrated tri-state circuitry with test means'
[patent_app_type] => 1
[patent_app_number] => 7/867475
[patent_app_country] => US
[patent_app_date] => 1992-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 12
[patent_no_of_words] => 7253
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/285/05285119.pdf
[firstpage_image] =>[orig_patent_app_number] => 867475
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/867475 | Semiconductor integrated tri-state circuitry with test means | Apr 12, 1992 | Issued |
| 07/861772 | ZAG FUSE FOR REDUCED BLOW-CURRENT APPLICATIONS | Apr 1, 1992 | Abandoned |
Array
(
[id] => 2899300
[patent_doc_number] => 05272397
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-12-21
[patent_title] => 'Basic DCVS circuits with dual function load circuits'
[patent_app_type] => 1
[patent_app_number] => 7/858790
[patent_app_country] => US
[patent_app_date] => 1992-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 10
[patent_no_of_words] => 7041
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/272/05272397.pdf
[firstpage_image] =>[orig_patent_app_number] => 858790
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/858790 | Basic DCVS circuits with dual function load circuits | Mar 26, 1992 | Issued |
Array
(
[id] => 3020072
[patent_doc_number] => 05341039
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-23
[patent_title] => 'High frequency integrated circuit device including a circuit for decreasing reflected signals in wiring formed on a semiconductor substrate'
[patent_app_type] => 1
[patent_app_number] => 7/858280
[patent_app_country] => US
[patent_app_date] => 1992-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3447
[patent_no_of_claims] => 22
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/341/05341039.pdf
[firstpage_image] =>[orig_patent_app_number] => 858280
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/858280 | High frequency integrated circuit device including a circuit for decreasing reflected signals in wiring formed on a semiconductor substrate | Mar 25, 1992 | Issued |