
Andrew Sanders
Examiner (ID: 1323)
| Most Active Art Unit | 2509 |
| Art Unit(s) | 2509, 2504 |
| Total Applications | 463 |
| Issued Applications | 431 |
| Pending Applications | 2 |
| Abandoned Applications | 30 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3062154
[patent_doc_number] => 05338982
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-16
[patent_title] => 'Programmable logic device'
[patent_app_type] => 1
[patent_app_number] => 7/857974
[patent_app_country] => US
[patent_app_date] => 1992-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 22
[patent_no_of_words] => 5638
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/338/05338982.pdf
[firstpage_image] =>[orig_patent_app_number] => 857974
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/857974 | Programmable logic device | Mar 25, 1992 | Issued |
Array
(
[id] => 3025364
[patent_doc_number] => 05327023
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-07-05
[patent_title] => 'Programmable logic device'
[patent_app_type] => 1
[patent_app_number] => 7/857986
[patent_app_country] => US
[patent_app_date] => 1992-03-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 2947
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/327/05327023.pdf
[firstpage_image] =>[orig_patent_app_number] => 857986
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/857986 | Programmable logic device | Mar 25, 1992 | Issued |
Array
(
[id] => 2901831
[patent_doc_number] => 05245228
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-09-14
[patent_title] => 'Level inverter circuit'
[patent_app_type] => 1
[patent_app_number] => 7/854379
[patent_app_country] => US
[patent_app_date] => 1992-03-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3644
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 526
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/245/05245228.pdf
[firstpage_image] =>[orig_patent_app_number] => 854379
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/854379 | Level inverter circuit | Mar 18, 1992 | Issued |
Array
(
[id] => 2983056
[patent_doc_number] => 05252863
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-12
[patent_title] => 'Drive circuit for use in a semiconductor integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 7/848372
[patent_app_country] => US
[patent_app_date] => 1992-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 5035
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/252/05252863.pdf
[firstpage_image] =>[orig_patent_app_number] => 848372
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/848372 | Drive circuit for use in a semiconductor integrated circuit | Mar 8, 1992 | Issued |
| 07/848098 | CIRCUIT FOR INTERCONNECTING INTEGRATED SEMICONDUCTOR CIRCUITS | Mar 8, 1992 | Abandoned |
| 07/847382 | PROGRAMMABLE APPLICATION SPECIFIC INTEGRATED CIRCUIT AND LOGIC CELL THEREFOR | Mar 5, 1992 | Abandoned |
Array
(
[id] => 2958502
[patent_doc_number] => 05231314
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-07-27
[patent_title] => 'Programmable timing circuit for integrated circuit device with test access port'
[patent_app_type] => 1
[patent_app_number] => 7/845387
[patent_app_country] => US
[patent_app_date] => 1992-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 4292
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 232
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/231/05231314.pdf
[firstpage_image] =>[orig_patent_app_number] => 845387
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/845387 | Programmable timing circuit for integrated circuit device with test access port | Mar 1, 1992 | Issued |
Array
(
[id] => 2968015
[patent_doc_number] => 05264744
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-23
[patent_title] => 'Complementary signal transmission circuit with impedance matching circuitry'
[patent_app_type] => 1
[patent_app_number] => 7/843214
[patent_app_country] => US
[patent_app_date] => 1992-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 7956
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/264/05264744.pdf
[firstpage_image] =>[orig_patent_app_number] => 843214
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/843214 | Complementary signal transmission circuit with impedance matching circuitry | Feb 27, 1992 | Issued |
Array
(
[id] => 2983126
[patent_doc_number] => 05252867
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-12
[patent_title] => 'Self-compensating digital delay semiconductor device with selectable output delays and method therefor'
[patent_app_type] => 1
[patent_app_number] => 7/843488
[patent_app_country] => US
[patent_app_date] => 1992-02-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2139
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 424
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/252/05252867.pdf
[firstpage_image] =>[orig_patent_app_number] => 843488
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/843488 | Self-compensating digital delay semiconductor device with selectable output delays and method therefor | Feb 27, 1992 | Issued |
Array
(
[id] => 2981464
[patent_doc_number] => 05256918
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-26
[patent_title] => 'Programmable logic circuit'
[patent_app_type] => 1
[patent_app_number] => 7/838889
[patent_app_country] => US
[patent_app_date] => 1992-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 3998
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 233
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/256/05256918.pdf
[firstpage_image] =>[orig_patent_app_number] => 838889
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/838889 | Programmable logic circuit | Feb 20, 1992 | Issued |
Array
(
[id] => 2991739
[patent_doc_number] => 05266849
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-30
[patent_title] => 'Tri state buffer circuit for dual power system'
[patent_app_type] => 1
[patent_app_number] => 7/839480
[patent_app_country] => US
[patent_app_date] => 1992-02-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2808
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/266/05266849.pdf
[firstpage_image] =>[orig_patent_app_number] => 839480
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/839480 | Tri state buffer circuit for dual power system | Feb 18, 1992 | Issued |
Array
(
[id] => 2981428
[patent_doc_number] => 05256916
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-26
[patent_title] => 'TTL to CMOS translating input buffer circuit with dual thresholds for high dynamic current and low static current'
[patent_app_type] => 1
[patent_app_number] => 7/838394
[patent_app_country] => US
[patent_app_date] => 1992-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 5078
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/256/05256916.pdf
[firstpage_image] =>[orig_patent_app_number] => 838394
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/838394 | TTL to CMOS translating input buffer circuit with dual thresholds for high dynamic current and low static current | Feb 17, 1992 | Issued |
Array
(
[id] => 2908602
[patent_doc_number] => 05248907
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-09-28
[patent_title] => 'Output buffer with controlled output level'
[patent_app_type] => 1
[patent_app_number] => 7/836582
[patent_app_country] => US
[patent_app_date] => 1992-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 7590
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/248/05248907.pdf
[firstpage_image] =>[orig_patent_app_number] => 836582
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/836582 | Output buffer with controlled output level | Feb 17, 1992 | Issued |
Array
(
[id] => 3015532
[patent_doc_number] => 05281874
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-25
[patent_title] => 'Compensated digital delay semiconductor device with selectable output taps and method therefor'
[patent_app_type] => 1
[patent_app_number] => 7/836078
[patent_app_country] => US
[patent_app_date] => 1992-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/281/05281874.pdf
[firstpage_image] =>[orig_patent_app_number] => 836078
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/836078 | Compensated digital delay semiconductor device with selectable output taps and method therefor | Feb 13, 1992 | Issued |
Array
(
[id] => 3069071
[patent_doc_number] => 05311074
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-10
[patent_title] => 'Semiconductor integrated circuit device with crosstalk prevention'
[patent_app_type] => 1
[patent_app_number] => 7/829373
[patent_app_country] => US
[patent_app_date] => 1992-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/311/05311074.pdf
[firstpage_image] =>[orig_patent_app_number] => 829373
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/829373 | Semiconductor integrated circuit device with crosstalk prevention | Feb 2, 1992 | Issued |
Array
(
[id] => 2989929
[patent_doc_number] => 05250857
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-05
[patent_title] => 'Dynamic logic circuit with reduced operating current'
[patent_app_type] => 1
[patent_app_number] => 7/825682
[patent_app_country] => US
[patent_app_date] => 1992-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3125
[patent_no_of_claims] => 10
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[patent_words_short_claim] => 281
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/250/05250857.pdf
[firstpage_image] =>[orig_patent_app_number] => 825682
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/825682 | Dynamic logic circuit with reduced operating current | Jan 26, 1992 | Issued |
Array
(
[id] => 2949189
[patent_doc_number] => 05254885
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-19
[patent_title] => 'Bi-CMOS logic circuit with feedback'
[patent_app_type] => 1
[patent_app_number] => 7/818094
[patent_app_country] => US
[patent_app_date] => 1992-01-08
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/254/05254885.pdf
[firstpage_image] =>[orig_patent_app_number] => 818094
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/818094 | Bi-CMOS logic circuit with feedback | Jan 7, 1992 | Issued |
Array
(
[id] => 2979990
[patent_doc_number] => 05208491
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-05-04
[patent_title] => 'Field programmable gate array'
[patent_app_type] => 1
[patent_app_number] => 7/817697
[patent_app_country] => US
[patent_app_date] => 1992-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/208/05208491.pdf
[firstpage_image] =>[orig_patent_app_number] => 817697
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/817697 | Field programmable gate array | Jan 6, 1992 | Issued |
Array
(
[id] => 2981411
[patent_doc_number] => 05256915
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-26
[patent_title] => 'Compound semiconductor integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 7/817092
[patent_app_country] => US
[patent_app_date] => 1992-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/256/05256915.pdf
[firstpage_image] =>[orig_patent_app_number] => 817092
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/817092 | Compound semiconductor integrated circuit | Jan 5, 1992 | Issued |
Array
(
[id] => 2938421
[patent_doc_number] => 05220216
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-06-15
[patent_title] => 'Programmable driving power of a CMOS gate'
[patent_app_type] => 1
[patent_app_number] => 7/816683
[patent_app_country] => US
[patent_app_date] => 1992-01-02
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/220/05220216.pdf
[firstpage_image] =>[orig_patent_app_number] => 816683
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/816683 | Programmable driving power of a CMOS gate | Jan 1, 1992 | Issued |