Andrew Sanders

Array ( [id] => 2916189 [patent_doc_number] => 05227679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-13 [patent_title] => 'Cmos digital-controlled delay gate' [patent_app_type] => 1 [patent_app_number] => 7/815791 [patent_app_country] => US [patent_app_date] => 1992-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3910 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/227/05227679.pdf [firstpage_image] =>[orig_patent_app_number] => 815791 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2936515 [patent_doc_number] => 05233238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-03 [patent_title] => 'High power buffer with increased current stability' [patent_app_type] => 1 [patent_app_number] => 7/812194 [patent_app_country] => US [patent_app_date] => 1991-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4091 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/233/05233238.pdf [firstpage_image] =>[orig_patent_app_number] => 812194 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3093254 [patent_doc_number] => 05278466 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-11 [patent_title] => 'Integrated circuit with reduced clock skew' [patent_app_type] => 1 [patent_app_number] => 7/812182 [patent_app_country] => US [patent_app_date] => 1991-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12168 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/278/05278466.pdf [firstpage_image] =>[orig_patent_app_number] => 812182 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2979696 [patent_doc_number] => 05194853 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-03-16 [patent_title] => 'Scanning circuit' [patent_app_type] => 1 [patent_app_number] => 7/810484 [patent_app_country] => US [patent_app_date] => 1991-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2689 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/194/05194853.pdf [firstpage_image] =>[orig_patent_app_number] => 810484 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2980703 [patent_doc_number] => 05225721 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'Signal translator for interconnecting CMOS and BiCMOS logic gates' [patent_app_type] => 1 [patent_app_number] => 7/809994 [patent_app_country] => US [patent_app_date] => 1991-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4177 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/225/05225721.pdf [firstpage_image] =>[orig_patent_app_number] => 809994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3052378 [patent_doc_number] => 05304867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-19 [patent_title] => 'CMOS input buffer with high speed and low power' [patent_app_type] => 1 [patent_app_number] => 7/806890 [patent_app_country] => US [patent_app_date] => 1991-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2000 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/304/05304867.pdf [firstpage_image] =>[orig_patent_app_number] => 806890 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2939404 [patent_doc_number] => 05229661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-20 [patent_title] => 'High speed bipolar digital logic gate architecture' [patent_app_type] => 1 [patent_app_number] => 7/806074 [patent_app_country] => US [patent_app_date] => 1991-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 5674 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/229/05229661.pdf [firstpage_image] =>[orig_patent_app_number] => 806074 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2980623 [patent_doc_number] => 05225717 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-06 [patent_title] => 'BiCMOS input buffer circuit operable at high speed under less power consumption' [patent_app_type] => 1 [patent_app_number] => 7/802682 [patent_app_country] => US [patent_app_date] => 1991-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5266 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/225/05225717.pdf [firstpage_image] =>[orig_patent_app_number] => 802682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3038516 [patent_doc_number] => 05329178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-12 [patent_title] => 'Integrated circuit device with user-programmable conditional power-down means' [patent_app_type] => 1 [patent_app_number] => 7/799499 [patent_app_country] => US [patent_app_date] => 1991-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2364 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/329/05329178.pdf [firstpage_image] =>[orig_patent_app_number] => 799499 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2799066 [patent_doc_number] => 05144168 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-01 [patent_title] => 'Self latching input buffer' [patent_app_type] => 1 [patent_app_number] => 7/799872 [patent_app_country] => US [patent_app_date] => 1991-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1722 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/144/05144168.pdf [firstpage_image] =>[orig_patent_app_number] => 799872 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3014927 [patent_doc_number] => 05276361 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-04 [patent_title] => 'TTL compatible input buffer' [patent_app_type] => 1 [patent_app_number] => 7/796993 [patent_app_country] => US [patent_app_date] => 1991-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2037 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/276/05276361.pdf [firstpage_image] =>[orig_patent_app_number] => 796993 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3015472 [patent_doc_number] => 05281871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-01-25 [patent_title] => 'Majority logic circuit' [patent_app_type] => 1 [patent_app_number] => 7/795472 [patent_app_country] => US [patent_app_date] => 1991-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5989 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/281/05281871.pdf [firstpage_image] =>[orig_patent_app_number] => 795472 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2925342 [patent_doc_number] => 05235218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-10 [patent_title] => 'Switching constant current source circuit' [patent_app_type] => 1 [patent_app_number] => 7/791379 [patent_app_country] => US [patent_app_date] => 1991-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2858 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/235/05235218.pdf [firstpage_image] =>[orig_patent_app_number] => 791379 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2926591 [patent_doc_number] => 05200652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-06 [patent_title] => 'Programmable/reprogrammable structure combining both antifuse and fuse elements' [patent_app_type] => 1 [patent_app_number] => 7/791797 [patent_app_country] => US [patent_app_date] => 1991-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1534 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/200/05200652.pdf [firstpage_image] =>[orig_patent_app_number] => 791797 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2941178 [patent_doc_number] => 05233483 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-08-03 [patent_title] => 'Magnetic write/read device' [patent_app_type] => 1 [patent_app_number] => 7/785054 [patent_app_country] => US [patent_app_date] => 1991-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 3695 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/233/05233483.pdf [firstpage_image] =>[orig_patent_app_number] => 785054 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2972830 [patent_doc_number] => 05202593 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-13 [patent_title] => 'Bi-directional bus repeater' [patent_app_type] => 1 [patent_app_number] => 7/785299 [patent_app_country] => US [patent_app_date] => 1991-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1893 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/202/05202593.pdf [firstpage_image] =>[orig_patent_app_number] => 785299 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2897357 [patent_doc_number] => 05210447 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-05-11 [patent_title] => 'Word decoder with SBD-T.sub.x clamp' [patent_app_type] => 1 [patent_app_number] => 7/784832 [patent_app_country] => US [patent_app_date] => 1991-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2612 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/210/05210447.pdf [firstpage_image] =>[orig_patent_app_number] => 784832 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3060173 [patent_doc_number] => 05307224 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-26 [patent_title] => 'Magnetic disk storage unit with magnetic head separating mechanism for separating float type magnetic head from magnetic disk' [patent_app_type] => 1 [patent_app_number] => 7/784370 [patent_app_country] => US [patent_app_date] => 1991-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 4287 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/307/05307224.pdf [firstpage_image] =>[orig_patent_app_number] => 784370 [rel_patent_id] =>[rel_patent_doc_number] =>)