
Andrew Sanders
Examiner (ID: 1323)
| Most Active Art Unit | 2509 |
| Art Unit(s) | 2509, 2504 |
| Total Applications | 463 |
| Issued Applications | 431 |
| Pending Applications | 2 |
| Abandoned Applications | 30 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2872372
[patent_doc_number] => 05153455
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-06
[patent_title] => 'Transition-based wired \"OR\" for VLSI systems'
[patent_app_type] => 1
[patent_app_number] => 7/772188
[patent_app_country] => US
[patent_app_date] => 1991-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 6136
[patent_no_of_claims] => 20
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[patent_words_short_claim] => 295
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/153/05153455.pdf
[firstpage_image] =>[orig_patent_app_number] => 772188
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/772188 | Transition-based wired "OR" for VLSI systems | Oct 6, 1991 | Issued |
Array
(
[id] => 2905197
[patent_doc_number] => 05218239
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-06-08
[patent_title] => 'Selectable edge rate CMOS output buffer circuit'
[patent_app_type] => 1
[patent_app_number] => 7/771391
[patent_app_country] => US
[patent_app_date] => 1991-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 4055
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/218/05218239.pdf
[firstpage_image] =>[orig_patent_app_number] => 771391
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/771391 | Selectable edge rate CMOS output buffer circuit | Oct 2, 1991 | Issued |
Array
(
[id] => 2981392
[patent_doc_number] => 05256914
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-26
[patent_title] => 'Short circuit protection circuit and method for output buffers'
[patent_app_type] => 1
[patent_app_number] => 7/771400
[patent_app_country] => US
[patent_app_date] => 1991-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 4211
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/256/05256914.pdf
[firstpage_image] =>[orig_patent_app_number] => 771400
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/771400 | Short circuit protection circuit and method for output buffers | Oct 2, 1991 | Issued |
Array
(
[id] => 2980685
[patent_doc_number] => 05225720
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-07-06
[patent_title] => 'Semiconductor integrated circuit device'
[patent_app_type] => 1
[patent_app_number] => 7/769438
[patent_app_country] => US
[patent_app_date] => 1991-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 14
[patent_no_of_words] => 5035
[patent_no_of_claims] => 11
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[patent_words_short_claim] => 115
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/225/05225720.pdf
[firstpage_image] =>[orig_patent_app_number] => 769438
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/769438 | Semiconductor integrated circuit device | Oct 2, 1991 | Issued |
Array
(
[id] => 2989965
[patent_doc_number] => 05250859
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-05
[patent_title] => 'Low power multifunction logic array'
[patent_app_type] => 1
[patent_app_number] => 7/767256
[patent_app_country] => US
[patent_app_date] => 1991-09-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 4144
[patent_no_of_claims] => 38
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/250/05250859.pdf
[firstpage_image] =>[orig_patent_app_number] => 767256
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/767256 | Low power multifunction logic array | Sep 26, 1991 | Issued |
Array
(
[id] => 2939422
[patent_doc_number] => 05229662
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-07-20
[patent_title] => 'Logic circuit capable of operating with any one of a plurality of alternative voltage supply levels'
[patent_app_type] => 1
[patent_app_number] => 7/765575
[patent_app_country] => US
[patent_app_date] => 1991-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 5132
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/229/05229662.pdf
[firstpage_image] =>[orig_patent_app_number] => 765575
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/765575 | Logic circuit capable of operating with any one of a plurality of alternative voltage supply levels | Sep 24, 1991 | Issued |
Array
(
[id] => 2794199
[patent_doc_number] => 05136185
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-04
[patent_title] => 'Local tristate control circuit'
[patent_app_type] => 1
[patent_app_number] => 7/763083
[patent_app_country] => US
[patent_app_date] => 1991-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 4128
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[pdf_file] => patents/05/136/05136185.pdf
[firstpage_image] =>[orig_patent_app_number] => 763083
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/763083 | Local tristate control circuit | Sep 19, 1991 | Issued |
Array
(
[id] => 3087472
[patent_doc_number] => 05280201
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-01-18
[patent_title] => 'Semiconductor logic circuit apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/760997
[patent_app_country] => US
[patent_app_date] => 1991-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 4392
[patent_no_of_claims] => 3
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[patent_words_short_claim] => 192
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/280/05280201.pdf
[firstpage_image] =>[orig_patent_app_number] => 760997
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/760997 | Semiconductor logic circuit apparatus | Sep 16, 1991 | Issued |
Array
(
[id] => 2925379
[patent_doc_number] => 05235220
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-10
[patent_title] => 'Majority decision method and circuit wherein least possible flip-flops are used'
[patent_app_type] => 1
[patent_app_number] => 7/760314
[patent_app_country] => US
[patent_app_date] => 1991-09-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 11738
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 184
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/235/05235220.pdf
[firstpage_image] =>[orig_patent_app_number] => 760314
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/760314 | Majority decision method and circuit wherein least possible flip-flops are used | Sep 15, 1991 | Issued |
Array
(
[id] => 2791120
[patent_doc_number] => 05155393
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-13
[patent_title] => 'Clock selection for storage elements of integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 7/755686
[patent_app_country] => US
[patent_app_date] => 1991-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 15
[patent_no_of_words] => 3284
[patent_no_of_claims] => 3
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[patent_words_short_claim] => 103
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/155/05155393.pdf
[firstpage_image] =>[orig_patent_app_number] => 755686
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/755686 | Clock selection for storage elements of integrated circuits | Sep 5, 1991 | Issued |
Array
(
[id] => 2824764
[patent_doc_number] => 05168178
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-12-01
[patent_title] => 'High speed NOR\'ing inverting, MUX\'ing and latching circuit with temperature compensated output noise control'
[patent_app_type] => 1
[patent_app_number] => 7/752780
[patent_app_country] => US
[patent_app_date] => 1991-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 5066
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/168/05168178.pdf
[firstpage_image] =>[orig_patent_app_number] => 752780
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/752780 | High speed NOR'ing inverting, MUX'ing and latching circuit with temperature compensated output noise control | Aug 29, 1991 | Issued |
Array
(
[id] => 2972788
[patent_doc_number] => 05202591
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-04-13
[patent_title] => 'Dynamic circuit disguise for microelectronic integrated digital logic circuits'
[patent_app_type] => 1
[patent_app_number] => 7/742799
[patent_app_country] => US
[patent_app_date] => 1991-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 4828
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/202/05202591.pdf
[firstpage_image] =>[orig_patent_app_number] => 742799
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/742799 | Dynamic circuit disguise for microelectronic integrated digital logic circuits | Aug 8, 1991 | Issued |
Array
(
[id] => 2932175
[patent_doc_number] => 05187392
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-02-16
[patent_title] => 'Programmable logic device with limited signal swing'
[patent_app_type] => 1
[patent_app_number] => 7/738783
[patent_app_country] => US
[patent_app_date] => 1991-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/05/187/05187392.pdf
[firstpage_image] =>[orig_patent_app_number] => 738783
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/738783 | Programmable logic device with limited signal swing | Jul 30, 1991 | Issued |
Array
(
[id] => 2959633
[patent_doc_number] => 05243226
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-09-07
[patent_title] => 'Programming of antifuses'
[patent_app_type] => 1
[patent_app_number] => 7/739076
[patent_app_country] => US
[patent_app_date] => 1991-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 8137
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/243/05243226.pdf
[firstpage_image] =>[orig_patent_app_number] => 739076
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/739076 | Programming of antifuses | Jul 30, 1991 | Issued |
Array
(
[id] => 2818343
[patent_doc_number] => 05122686
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-06-16
[patent_title] => 'Power reduction design for ECL outputs that is independent of random termination voltage'
[patent_app_type] => 1
[patent_app_number] => 7/732383
[patent_app_country] => US
[patent_app_date] => 1991-07-18
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[pdf_file] => patents/05/122/05122686.pdf
[firstpage_image] =>[orig_patent_app_number] => 732383
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/732383 | Power reduction design for ECL outputs that is independent of random termination voltage | Jul 17, 1991 | Issued |
Array
(
[id] => 2787713
[patent_doc_number] => 05164613
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-11-17
[patent_title] => 'Reset monitor'
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[patent_app_number] => 7/731287
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[patent_app_date] => 1991-07-16
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/164/05164613.pdf
[firstpage_image] =>[orig_patent_app_number] => 731287
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/731287 | Reset monitor | Jul 15, 1991 | Issued |
Array
(
[id] => 2825862
[patent_doc_number] => 05173621
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-12-22
[patent_title] => 'Transceiver with isolated power rails for ground bounce reduction'
[patent_app_type] => 1
[patent_app_number] => 7/728988
[patent_app_country] => US
[patent_app_date] => 1991-07-12
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/173/05173621.pdf
[firstpage_image] =>[orig_patent_app_number] => 728988
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/728988 | Transceiver with isolated power rails for ground bounce reduction | Jul 11, 1991 | Issued |
Array
(
[id] => 2967307
[patent_doc_number] => 05274283
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-12-28
[patent_title] => 'Compound semiconductor integrated circuit device'
[patent_app_type] => 1
[patent_app_number] => 7/726183
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[pdf_file] => patents/05/274/05274283.pdf
[firstpage_image] =>[orig_patent_app_number] => 726183
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/726183 | Compound semiconductor integrated circuit device | Jul 4, 1991 | Issued |
Array
(
[id] => 2810489
[patent_doc_number] => 05157279
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-20
[patent_title] => 'Data output driver with substrate biasing producing high output gain'
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[patent_app_number] => 7/724889
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[pdf_file] => patents/05/157/05157279.pdf
[firstpage_image] =>[orig_patent_app_number] => 724889
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/724889 | Data output driver with substrate biasing producing high output gain | Jul 1, 1991 | Issued |
Array
(
[id] => 2989912
[patent_doc_number] => 05250856
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-10-05
[patent_title] => 'Differential input buffer-inverters and gates'
[patent_app_type] => 1
[patent_app_number] => 7/863551
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/250/05250856.pdf
[firstpage_image] =>[orig_patent_app_number] => 863551
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/863551 | Differential input buffer-inverters and gates | Jun 30, 1991 | Issued |