
Andrew Sanders
Examiner (ID: 1323)
| Most Active Art Unit | 2509 |
| Art Unit(s) | 2509, 2504 |
| Total Applications | 463 |
| Issued Applications | 431 |
| Pending Applications | 2 |
| Abandoned Applications | 30 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2924535
[patent_doc_number] => 05192881
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-09
[patent_title] => 'Circuit which reduces noise caused by high current outputs'
[patent_app_type] => 1
[patent_app_number] => 7/723110
[patent_app_country] => US
[patent_app_date] => 1991-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3494
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 301
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/192/05192881.pdf
[firstpage_image] =>[orig_patent_app_number] => 723110
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/723110 | Circuit which reduces noise caused by high current outputs | Jun 27, 1991 | Issued |
| 07/722991 | APPARATUS AND METHOD FOR ECL-LIKE SIGNAL TO CMOS SIGNAL CONVERSION | Jun 27, 1991 | Abandoned |
Array
(
[id] => 2845065
[patent_doc_number] => 05172016
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-12-15
[patent_title] => 'Five-volt tolerant differential receiver'
[patent_app_type] => 1
[patent_app_number] => 7/724407
[patent_app_country] => US
[patent_app_date] => 1991-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 1292
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/172/05172016.pdf
[firstpage_image] =>[orig_patent_app_number] => 724407
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/724407 | Five-volt tolerant differential receiver | Jun 27, 1991 | Issued |
Array
(
[id] => 2810022
[patent_doc_number] => 05148112
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-15
[patent_title] => 'Efficient arbiter'
[patent_app_type] => 1
[patent_app_number] => 7/723055
[patent_app_country] => US
[patent_app_date] => 1991-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5184
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/148/05148112.pdf
[firstpage_image] =>[orig_patent_app_number] => 723055
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/723055 | Efficient arbiter | Jun 27, 1991 | Issued |
Array
(
[id] => 3450513
[patent_doc_number] => 05387824
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-07
[patent_title] => 'Variable drive output buffer circuit'
[patent_app_type] => 1
[patent_app_number] => 7/718735
[patent_app_country] => US
[patent_app_date] => 1991-06-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3915
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 315
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/387/05387824.pdf
[firstpage_image] =>[orig_patent_app_number] => 718735
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/718735 | Variable drive output buffer circuit | Jun 20, 1991 | Issued |
Array
(
[id] => 2882079
[patent_doc_number] => 05118972
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-06-02
[patent_title] => 'BiCMOS gate pull-down circuit'
[patent_app_type] => 1
[patent_app_number] => 7/714481
[patent_app_country] => US
[patent_app_date] => 1991-06-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3053
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 243
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/118/05118972.pdf
[firstpage_image] =>[orig_patent_app_number] => 714481
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/714481 | BiCMOS gate pull-down circuit | Jun 12, 1991 | Issued |
| 07/714190 | PRE-CHARGE TRIGGERING TO INCREASE THROUGHPUT BY INITIATING REGISTER OUTPUT AT BEGINNING OF PRE-CHARGE PHASE | Jun 11, 1991 | Abandoned |
Array
(
[id] => 2863666
[patent_doc_number] => 05149991
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-22
[patent_title] => 'Ground bounce blocking output buffer circuit'
[patent_app_type] => 1
[patent_app_number] => 7/711313
[patent_app_country] => US
[patent_app_date] => 1991-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 5504
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 324
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/149/05149991.pdf
[firstpage_image] =>[orig_patent_app_number] => 711313
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/711313 | Ground bounce blocking output buffer circuit | Jun 5, 1991 | Issued |
Array
(
[id] => 2863551
[patent_doc_number] => 05166547
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-11-24
[patent_title] => 'Programmable DCVS logic circuits'
[patent_app_type] => 1
[patent_app_number] => 7/711487
[patent_app_country] => US
[patent_app_date] => 1991-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 18
[patent_no_of_words] => 8023
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/166/05166547.pdf
[firstpage_image] =>[orig_patent_app_number] => 711487
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/711487 | Programmable DCVS logic circuits | Jun 4, 1991 | Issued |
Array
(
[id] => 2943526
[patent_doc_number] => 05191240
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-03-02
[patent_title] => 'BiCMOS driver circuits with improved low output level'
[patent_app_type] => 1
[patent_app_number] => 7/710592
[patent_app_country] => US
[patent_app_date] => 1991-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 7
[patent_no_of_words] => 3967
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/191/05191240.pdf
[firstpage_image] =>[orig_patent_app_number] => 710592
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/710592 | BiCMOS driver circuits with improved low output level | Jun 4, 1991 | Issued |
Array
(
[id] => 2893948
[patent_doc_number] => 05239211
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-08-24
[patent_title] => 'Output buffer circuit'
[patent_app_type] => 1
[patent_app_number] => 7/709190
[patent_app_country] => US
[patent_app_date] => 1991-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 5073
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 144
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/239/05239211.pdf
[firstpage_image] =>[orig_patent_app_number] => 709190
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/709190 | Output buffer circuit | Jun 2, 1991 | Issued |
| 07/709241 | PROGRAMMABLE CELL WITH A PROGRAMMABLE COMPONENT OUTSIDE THE SIGNAL PATH | Jun 2, 1991 | Abandoned |
Array
(
[id] => 2856619
[patent_doc_number] => 05134317
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-07-28
[patent_title] => 'Booster circuit for a semiconductor memory device'
[patent_app_type] => 1
[patent_app_number] => 7/705618
[patent_app_country] => US
[patent_app_date] => 1991-05-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3060
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 210
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/134/05134317.pdf
[firstpage_image] =>[orig_patent_app_number] => 705618
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/705618 | Booster circuit for a semiconductor memory device | May 28, 1991 | Issued |
Array
(
[id] => 2846981
[patent_doc_number] => 05138197
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-11
[patent_title] => 'Address decoder array composed of CMOS'
[patent_app_type] => 1
[patent_app_number] => 7/704215
[patent_app_country] => US
[patent_app_date] => 1991-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4380
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/138/05138197.pdf
[firstpage_image] =>[orig_patent_app_number] => 704215
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/704215 | Address decoder array composed of CMOS | May 21, 1991 | Issued |
Array
(
[id] => 2846962
[patent_doc_number] => 05138196
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-11
[patent_title] => 'Integrated semiconductor circuit'
[patent_app_type] => 1
[patent_app_number] => 7/701810
[patent_app_country] => US
[patent_app_date] => 1991-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3297
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 284
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/138/05138196.pdf
[firstpage_image] =>[orig_patent_app_number] => 701810
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/701810 | Integrated semiconductor circuit | May 18, 1991 | Issued |
Array
(
[id] => 2793016
[patent_doc_number] => 05101120
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-03-31
[patent_title] => 'BiCMOS output driver'
[patent_app_type] => 1
[patent_app_number] => 7/701392
[patent_app_country] => US
[patent_app_date] => 1991-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2216
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/101/05101120.pdf
[firstpage_image] =>[orig_patent_app_number] => 701392
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/701392 | BiCMOS output driver | May 15, 1991 | Issued |
Array
(
[id] => 2799047
[patent_doc_number] => 05144167
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-01
[patent_title] => 'Zero power, high impedance TTL-to-CMOS converter'
[patent_app_type] => 1
[patent_app_number] => 7/701686
[patent_app_country] => US
[patent_app_date] => 1991-05-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 1381
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 277
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/144/05144167.pdf
[firstpage_image] =>[orig_patent_app_number] => 701686
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/701686 | Zero power, high impedance TTL-to-CMOS converter | May 9, 1991 | Issued |
Array
(
[id] => 2897930
[patent_doc_number] => 05177378
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-01-05
[patent_title] => 'Source-coupled FET logic circuit'
[patent_app_type] => 1
[patent_app_number] => 7/696743
[patent_app_country] => US
[patent_app_date] => 1991-05-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3322
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 324
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/177/05177378.pdf
[firstpage_image] =>[orig_patent_app_number] => 696743
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/696743 | Source-coupled FET logic circuit | May 6, 1991 | Issued |
Array
(
[id] => 2803542
[patent_doc_number] => 05140190
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-18
[patent_title] => 'Output circuit for a bipolar complementary metal oxide semiconductor'
[patent_app_type] => 1
[patent_app_number] => 7/696220
[patent_app_country] => US
[patent_app_date] => 1991-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 2475
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 271
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/140/05140190.pdf
[firstpage_image] =>[orig_patent_app_number] => 696220
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/696220 | Output circuit for a bipolar complementary metal oxide semiconductor | May 5, 1991 | Issued |
Array
(
[id] => 2859631
[patent_doc_number] => 05113097
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-05-12
[patent_title] => 'CMOS level shifter circuit'
[patent_app_type] => 1
[patent_app_number] => 7/696981
[patent_app_country] => US
[patent_app_date] => 1991-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 3399
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/113/05113097.pdf
[firstpage_image] =>[orig_patent_app_number] => 696981
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/696981 | CMOS level shifter circuit | May 1, 1991 | Issued |