Andrew Sanders

Array ( [id] => 2939337 [patent_doc_number] => 05229657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-20 [patent_title] => 'Method and apparatus for controlling simultaneous switching output noise in boundary scan paths' [patent_app_type] => 1 [patent_app_number] => 7/694532 [patent_app_country] => US [patent_app_date] => 1991-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5092 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/229/05229657.pdf [firstpage_image] =>[orig_patent_app_number] => 694532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2835779 [patent_doc_number] => 05175447 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-29 [patent_title] => 'Multifunctional scan flip-flop' [patent_app_type] => 1 [patent_app_number] => 7/687616 [patent_app_country] => US [patent_app_date] => 1991-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4237 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/175/05175447.pdf [firstpage_image] =>[orig_patent_app_number] => 687616 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2827746 [patent_doc_number] => 05095228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-10 [patent_title] => 'Circuits for preventing breakdown of low-voltage device inputs during high voltage antifuse programming' [patent_app_type] => 1 [patent_app_number] => 7/687980 [patent_app_country] => US [patent_app_date] => 1991-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3030 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/095/05095228.pdf [firstpage_image] =>[orig_patent_app_number] => 687980 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2946548 [patent_doc_number] => 05223744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-06-29 [patent_title] => 'Semiconductor integrated circuit with circuits for generating stable reference potential' [patent_app_type] => 1 [patent_app_number] => 7/680185 [patent_app_country] => US [patent_app_date] => 1991-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 24 [patent_no_of_words] => 15482 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/223/05223744.pdf [firstpage_image] =>[orig_patent_app_number] => 680185 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2859613 [patent_doc_number] => 05113096 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-12 [patent_title] => 'BiCMOS circuit' [patent_app_type] => 1 [patent_app_number] => 7/679637 [patent_app_country] => US [patent_app_date] => 1991-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5771 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/113/05113096.pdf [firstpage_image] =>[orig_patent_app_number] => 679637 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2790168 [patent_doc_number] => 05130575 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-14 [patent_title] => 'Testable latch self checker' [patent_app_type] => 1 [patent_app_number] => 7/675747 [patent_app_country] => US [patent_app_date] => 1991-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5491 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 249 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/130/05130575.pdf [firstpage_image] =>[orig_patent_app_number] => 675747 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2822689 [patent_doc_number] => 05081376 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-14 [patent_title] => 'Level converter for converting ECL-level signal voltage to TTL-level signal voltage' [patent_app_type] => 1 [patent_app_number] => 7/674786 [patent_app_country] => US [patent_app_date] => 1991-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2454 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/081/05081376.pdf [firstpage_image] =>[orig_patent_app_number] => 674786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2859596 [patent_doc_number] => 05113095 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-12 [patent_title] => 'BiCMOS logic circuit with a CML output' [patent_app_type] => 1 [patent_app_number] => 7/675042 [patent_app_country] => US [patent_app_date] => 1991-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5486 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/113/05113095.pdf [firstpage_image] =>[orig_patent_app_number] => 675042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2852073 [patent_doc_number] => 05111077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-05 [patent_title] => 'BiCMOS noninverting buffer and logic gates' [patent_app_type] => 1 [patent_app_number] => 7/673648 [patent_app_country] => US [patent_app_date] => 1991-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4830 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/111/05111077.pdf [firstpage_image] =>[orig_patent_app_number] => 673648 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2819725 [patent_doc_number] => 05122757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-16 [patent_title] => 'Digital frequency generator' [patent_app_type] => 1 [patent_app_number] => 7/673841 [patent_app_country] => US [patent_app_date] => 1991-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2591 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/122/05122757.pdf [firstpage_image] =>[orig_patent_app_number] => 673841 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2874105 [patent_doc_number] => 05162676 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-10 [patent_title] => 'Circuit having level converting circuit for converting logic level' [patent_app_type] => 1 [patent_app_number] => 7/669987 [patent_app_country] => US [patent_app_date] => 1991-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3031 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/162/05162676.pdf [firstpage_image] =>[orig_patent_app_number] => 669987 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2834762 [patent_doc_number] => 05099151 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-24 [patent_title] => 'Buffer circuit for logic level conversion' [patent_app_type] => 1 [patent_app_number] => 7/669152 [patent_app_country] => US [patent_app_date] => 1991-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 5059 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 434 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/099/05099151.pdf [firstpage_image] =>[orig_patent_app_number] => 669152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2880929 [patent_doc_number] => 05159208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-27 [patent_title] => 'Interface circuit provided between a compound semiconductor logic circuit and a bipolar transistor circuit' [patent_app_type] => 1 [patent_app_number] => 7/666619 [patent_app_country] => US [patent_app_date] => 1991-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 5086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/159/05159208.pdf [firstpage_image] =>[orig_patent_app_number] => 666619 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2845048 [patent_doc_number] => 05172015 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-15 [patent_title] => 'Integratable transistor circuit for outputting logical levels' [patent_app_type] => 1 [patent_app_number] => 7/665782 [patent_app_country] => US [patent_app_date] => 1991-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3605 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/172/05172015.pdf [firstpage_image] =>[orig_patent_app_number] => 665782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2886360 [patent_doc_number] => 05109168 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-28 [patent_title] => 'Method and apparatus for the design and optimization of a balanced tree for clock distribution in computer integrated circuits' [patent_app_type] => 1 [patent_app_number] => 7/661896 [patent_app_country] => US [patent_app_date] => 1991-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3364 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/109/05109168.pdf [firstpage_image] =>[orig_patent_app_number] => 661896 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2901798 [patent_doc_number] => 05245226 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-14 [patent_title] => 'Output logic macrocell' [patent_app_type] => 1 [patent_app_number] => 7/661285 [patent_app_country] => US [patent_app_date] => 1991-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3205 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/245/05245226.pdf [firstpage_image] =>[orig_patent_app_number] => 661285 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2835761 [patent_doc_number] => 05175446 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-12-29 [patent_title] => 'Demultiplexer including a three-state gate' [patent_app_type] => 1 [patent_app_number] => 7/655498 [patent_app_country] => US [patent_app_date] => 1991-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1990 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/175/05175446.pdf [firstpage_image] =>[orig_patent_app_number] => 655498 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2856585 [patent_doc_number] => 05134315 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-28 [patent_title] => 'Synchronous counter terminal count output circuit' [patent_app_type] => 1 [patent_app_number] => 7/652588 [patent_app_country] => US [patent_app_date] => 1991-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3316 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/134/05134315.pdf [firstpage_image] =>[orig_patent_app_number] => 652588 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2834784 [patent_doc_number] => 05099152 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-03-24 [patent_title] => 'Superconducting circuit having an output conversion circuit' [patent_app_type] => 1 [patent_app_number] => 7/651528 [patent_app_country] => US [patent_app_date] => 1991-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 6315 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/099/05099152.pdf [firstpage_image] =>[orig_patent_app_number] => 651528 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2940082 [patent_doc_number] => 05247212 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-09-21 [patent_title] => 'Complementary logic input parallel (CLIP) logic circuit family' [patent_app_type] => 1 [patent_app_number] => 7/648219 [patent_app_country] => US [patent_app_date] => 1991-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 7187 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/247/05247212.pdf [firstpage_image] =>[orig_patent_app_number] => 648219 [rel_patent_id] =>[rel_patent_doc_number] =>)