Andrew Sanders

Array ( [id] => 2984108 [patent_doc_number] => 05204559 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-04-20 [patent_title] => 'Method and apparatus for controlling clock skew' [patent_app_type] => 1 [patent_app_number] => 7/645981 [patent_app_country] => US [patent_app_date] => 1991-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 9388 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/204/05204559.pdf [firstpage_image] =>[orig_patent_app_number] => 645981 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2939389 [patent_doc_number] => 05229660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-07-20 [patent_title] => 'Integrated circuit with means to prevent its logic output circuit breakdown' [patent_app_type] => 1 [patent_app_number] => 7/644780 [patent_app_country] => US [patent_app_date] => 1991-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4136 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/229/05229660.pdf [firstpage_image] =>[orig_patent_app_number] => 644780 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3450557 [patent_doc_number] => 05387827 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-02-07 [patent_title] => 'Semiconductor integrated circuit having logic gates' [patent_app_type] => 1 [patent_app_number] => 7/643372 [patent_app_country] => US [patent_app_date] => 1991-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 31 [patent_no_of_words] => 11210 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/387/05387827.pdf [firstpage_image] =>[orig_patent_app_number] => 643372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2790186 [patent_doc_number] => 05130576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-14 [patent_title] => 'Synchronous ECL to CMOS translator' [patent_app_type] => 1 [patent_app_number] => 7/641984 [patent_app_country] => US [patent_app_date] => 1991-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1609 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/130/05130576.pdf [firstpage_image] =>[orig_patent_app_number] => 641984 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2791075 [patent_doc_number] => 05155391 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-13 [patent_title] => 'Synchronous internal clock distribution' [patent_app_type] => 1 [patent_app_number] => 7/642098 [patent_app_country] => US [patent_app_date] => 1991-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1238 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/155/05155391.pdf [firstpage_image] =>[orig_patent_app_number] => 642098 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2718734 [patent_doc_number] => 05053652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-01 [patent_title] => 'High speed sensor system using a level shift circuit' [patent_app_type] => 1 [patent_app_number] => 7/637591 [patent_app_country] => US [patent_app_date] => 1991-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 30 [patent_no_of_words] => 22210 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/053/05053652.pdf [firstpage_image] =>[orig_patent_app_number] => 637591 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2886342 [patent_doc_number] => 05109167 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-28 [patent_title] => 'PNP word line driver' [patent_app_type] => 1 [patent_app_number] => 7/635865 [patent_app_country] => US [patent_app_date] => 1990-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6722 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/109/05109167.pdf [firstpage_image] =>[orig_patent_app_number] => 635865 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3055294 [patent_doc_number] => 05283481 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-02-01 [patent_title] => 'Bipolar element bifet array decoder' [patent_app_type] => 1 [patent_app_number] => 7/633771 [patent_app_country] => US [patent_app_date] => 1990-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6297 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/283/05283481.pdf [firstpage_image] =>[orig_patent_app_number] => 633771 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2852144 [patent_doc_number] => 05111081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-05 [patent_title] => 'Process compensated input switching threshold of a CMOS receiver' [patent_app_type] => 1 [patent_app_number] => 7/630576 [patent_app_country] => US [patent_app_date] => 1990-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3246 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/111/05111081.pdf [firstpage_image] =>[orig_patent_app_number] => 630576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2791023 [patent_doc_number] => 05155388 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-13 [patent_title] => 'Logic gates with controllable time delay' [patent_app_type] => 1 [patent_app_number] => 7/632275 [patent_app_country] => US [patent_app_date] => 1990-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2902 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 356 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/155/05155388.pdf [firstpage_image] =>[orig_patent_app_number] => 632275 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2831442 [patent_doc_number] => 05117133 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-26 [patent_title] => 'Hashing output exclusive-OR driver with precharge' [patent_app_type] => 1 [patent_app_number] => 7/629291 [patent_app_country] => US [patent_app_date] => 1990-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2405 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/117/05117133.pdf [firstpage_image] =>[orig_patent_app_number] => 629291 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2799010 [patent_doc_number] => 05144165 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-01 [patent_title] => 'CMOS off-chip driver circuits' [patent_app_type] => 1 [patent_app_number] => 7/628255 [patent_app_country] => US [patent_app_date] => 1990-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3346 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/144/05144165.pdf [firstpage_image] =>[orig_patent_app_number] => 628255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2672647 [patent_doc_number] => 05070261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-03 [patent_title] => 'Apparatus and method for translating voltages' [patent_app_type] => 1 [patent_app_number] => 7/622046 [patent_app_country] => US [patent_app_date] => 1990-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3796 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/070/05070261.pdf [firstpage_image] =>[orig_patent_app_number] => 622046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2998943 [patent_doc_number] => 05367207 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'Structure and method for programming antifuses in an integrated circuit array' [patent_app_type] => 1 [patent_app_number] => 7/625732 [patent_app_country] => US [patent_app_date] => 1990-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 8015 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/367/05367207.pdf [firstpage_image] =>[orig_patent_app_number] => 625732 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2967997 [patent_doc_number] => 05264743 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-11-23 [patent_title] => 'Semiconductor memory operating with low supply voltage' [patent_app_type] => 1 [patent_app_number] => 7/621064 [patent_app_country] => US [patent_app_date] => 1990-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 47 [patent_no_of_words] => 17146 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 570 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/264/05264743.pdf [firstpage_image] =>[orig_patent_app_number] => 621064 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2769001 [patent_doc_number] => 05063312 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-05 [patent_title] => 'Delay circuit with adjustable delay' [patent_app_type] => 1 [patent_app_number] => 7/618778 [patent_app_country] => US [patent_app_date] => 1990-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2546 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/063/05063312.pdf [firstpage_image] =>[orig_patent_app_number] => 618778 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2778877 [patent_doc_number] => 05132573 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-21 [patent_title] => 'Semiconductor gate array device compatible with ECL signals and/or TTL signals' [patent_app_type] => 1 [patent_app_number] => 7/618691 [patent_app_country] => US [patent_app_date] => 1990-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 28 [patent_no_of_words] => 12772 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/132/05132573.pdf [firstpage_image] =>[orig_patent_app_number] => 618691 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2790275 [patent_doc_number] => 05130581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-14 [patent_title] => 'Sense amplifier in a dynamic RAM having double power lines' [patent_app_type] => 1 [patent_app_number] => 7/615879 [patent_app_country] => US [patent_app_date] => 1990-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5406 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 871 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/130/05130581.pdf [firstpage_image] =>[orig_patent_app_number] => 615879 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2840999 [patent_doc_number] => 05121015 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-09 [patent_title] => 'Voltage controlled delay element' [patent_app_type] => 1 [patent_app_number] => 7/613178 [patent_app_country] => US [patent_app_date] => 1990-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3548 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/121/05121015.pdf [firstpage_image] =>[orig_patent_app_number] => 613178 [rel_patent_id] =>[rel_patent_doc_number] =>)