Search

Andrew Sanders

Examiner (ID: 6460)

Most Active Art Unit
2509
Art Unit(s)
2509, 2504
Total Applications
463
Issued Applications
431
Pending Applications
2
Abandoned Applications
30

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3519013 [patent_doc_number] => 05512844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-30 [patent_title] => 'Output circuit with high output voltage protection means' [patent_app_type] => 1 [patent_app_number] => 8/501739 [patent_app_country] => US [patent_app_date] => 1995-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 33 [patent_no_of_words] => 6882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/512/05512844.pdf [firstpage_image] =>[orig_patent_app_number] => 501739 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/501739
Output circuit with high output voltage protection means Jul 11, 1995 Issued
Array ( [id] => 3595953 [patent_doc_number] => 05568061 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-22 [patent_title] => 'Redundant line decoder master enable' [patent_app_type] => 1 [patent_app_number] => 8/492219 [patent_app_country] => US [patent_app_date] => 1995-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2363 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/568/05568061.pdf [firstpage_image] =>[orig_patent_app_number] => 492219 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/492219
Redundant line decoder master enable Jun 18, 1995 Issued
Array ( [id] => 3539293 [patent_doc_number] => 05557219 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-17 [patent_title] => 'Interface level programmability' [patent_app_type] => 1 [patent_app_number] => 8/456436 [patent_app_country] => US [patent_app_date] => 1995-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 3013 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/557/05557219.pdf [firstpage_image] =>[orig_patent_app_number] => 456436 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/456436
Interface level programmability May 31, 1995 Issued
Array ( [id] => 3512568 [patent_doc_number] => 05570046 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-29 [patent_title] => 'Lead frame with noisy and quiet V.sub.SS and V.sub.DD leads' [patent_app_type] => 1 [patent_app_number] => 8/453184 [patent_app_country] => US [patent_app_date] => 1995-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6023 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/570/05570046.pdf [firstpage_image] =>[orig_patent_app_number] => 453184 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/453184
Lead frame with noisy and quiet V.sub.SS and V.sub.DD leads May 29, 1995 Issued
Array ( [id] => 3560500 [patent_doc_number] => 05543732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-06 [patent_title] => 'Programmable logic array devices with interconnect lines of various lengths' [patent_app_type] => 1 [patent_app_number] => 8/442832 [patent_app_country] => US [patent_app_date] => 1995-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4747 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/543/05543732.pdf [firstpage_image] =>[orig_patent_app_number] => 442832 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/442832
Programmable logic array devices with interconnect lines of various lengths May 16, 1995 Issued
Array ( [id] => 3530662 [patent_doc_number] => 05528173 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-06-18 [patent_title] => 'Low power, high speed level shifter' [patent_app_type] => 1 [patent_app_number] => 8/438645 [patent_app_country] => US [patent_app_date] => 1995-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2619 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/528/05528173.pdf [firstpage_image] =>[orig_patent_app_number] => 438645 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/438645
Low power, high speed level shifter May 9, 1995 Issued
Array ( [id] => 3532145 [patent_doc_number] => 05541533 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-30 [patent_title] => 'Output circuit for an TTL-CMOS integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/432926 [patent_app_country] => US [patent_app_date] => 1995-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4465 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/541/05541533.pdf [firstpage_image] =>[orig_patent_app_number] => 432926 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/432926
Output circuit for an TTL-CMOS integrated circuit Apr 30, 1995 Issued
Array ( [id] => 3562847 [patent_doc_number] => 05502404 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-26 [patent_title] => 'Gate array cell with predefined connection patterns' [patent_app_type] => 1 [patent_app_number] => 8/431233 [patent_app_country] => US [patent_app_date] => 1995-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2181 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/502/05502404.pdf [firstpage_image] =>[orig_patent_app_number] => 431233 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/431233
Gate array cell with predefined connection patterns Apr 27, 1995 Issued
Array ( [id] => 3596852 [patent_doc_number] => 05488316 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-30 [patent_title] => 'Circuit for selecting a bit in a look-up table' [patent_app_type] => 1 [patent_app_number] => 8/429434 [patent_app_country] => US [patent_app_date] => 1995-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 6422 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/488/05488316.pdf [firstpage_image] =>[orig_patent_app_number] => 429434 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/429434
Circuit for selecting a bit in a look-up table Apr 25, 1995 Issued
Array ( [id] => 3628081 [patent_doc_number] => 05594368 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'Low power combinational logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/423943 [patent_app_country] => US [patent_app_date] => 1995-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4487 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/594/05594368.pdf [firstpage_image] =>[orig_patent_app_number] => 423943 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/423943
Low power combinational logic circuit Apr 18, 1995 Issued
Array ( [id] => 3545161 [patent_doc_number] => 05481207 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'High speed, low power input/output circuit for a multi-chip module' [patent_app_type] => 1 [patent_app_number] => 8/427916 [patent_app_country] => US [patent_app_date] => 1995-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4383 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/481/05481207.pdf [firstpage_image] =>[orig_patent_app_number] => 427916 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/427916
High speed, low power input/output circuit for a multi-chip module Apr 18, 1995 Issued
Array ( [id] => 3543119 [patent_doc_number] => 05495188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'Pulsed static CMOS circuit' [patent_app_type] => 1 [patent_app_number] => 8/421343 [patent_app_country] => US [patent_app_date] => 1995-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1879 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/495/05495188.pdf [firstpage_image] =>[orig_patent_app_number] => 421343 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/421343
Pulsed static CMOS circuit Apr 12, 1995 Issued
Array ( [id] => 3555814 [patent_doc_number] => 05572150 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-05 [patent_title] => 'Low power pre-discharged ratio logic' [patent_app_type] => 1 [patent_app_number] => 8/419630 [patent_app_country] => US [patent_app_date] => 1995-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5742 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/572/05572150.pdf [firstpage_image] =>[orig_patent_app_number] => 419630 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/419630
Low power pre-discharged ratio logic Apr 9, 1995 Issued
Array ( [id] => 3619751 [patent_doc_number] => 05510729 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-23 [patent_title] => 'Output characteristics stabilization of CMOS devices' [patent_app_type] => 1 [patent_app_number] => 8/411342 [patent_app_country] => US [patent_app_date] => 1995-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6606 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/510/05510729.pdf [firstpage_image] =>[orig_patent_app_number] => 411342 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/411342
Output characteristics stabilization of CMOS devices Mar 26, 1995 Issued
Array ( [id] => 3526582 [patent_doc_number] => 05489856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Laser-programmable clocked-logic integrated-circuit' [patent_app_type] => 1 [patent_app_number] => 8/409233 [patent_app_country] => US [patent_app_date] => 1995-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3562 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 1013 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/489/05489856.pdf [firstpage_image] =>[orig_patent_app_number] => 409233 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/409233
Laser-programmable clocked-logic integrated-circuit Mar 23, 1995 Issued
08/398843 EMITTER COUPLED LOGIC CIRCUIT Mar 5, 1995 Abandoned
Array ( [id] => 3543034 [patent_doc_number] => 05495182 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-27 [patent_title] => 'Fast-fully restoring polarity control circuit' [patent_app_type] => 1 [patent_app_number] => 8/395733 [patent_app_country] => US [patent_app_date] => 1995-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1089 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/495/05495182.pdf [firstpage_image] =>[orig_patent_app_number] => 395733 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/395733
Fast-fully restoring polarity control circuit Feb 27, 1995 Issued
Array ( [id] => 3576944 [patent_doc_number] => 05539329 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-23 [patent_title] => 'Programmable logic circuit w/neuron MOS transistors' [patent_app_type] => 1 [patent_app_number] => 8/387844 [patent_app_country] => US [patent_app_date] => 1995-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 4629 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/539/05539329.pdf [firstpage_image] =>[orig_patent_app_number] => 387844 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/387844
Programmable logic circuit w/neuron MOS transistors Feb 20, 1995 Issued
Array ( [id] => 3519027 [patent_doc_number] => 05512845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-04-30 [patent_title] => 'Bootstrap circuit' [patent_app_type] => 1 [patent_app_number] => 8/389227 [patent_app_country] => US [patent_app_date] => 1995-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2765 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/512/05512845.pdf [firstpage_image] =>[orig_patent_app_number] => 389227 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/389227
Bootstrap circuit Feb 14, 1995 Issued
Array ( [id] => 3424530 [patent_doc_number] => 05479115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-12-26 [patent_title] => 'Signal processing device and level converter circuit' [patent_app_type] => 1 [patent_app_number] => 8/388433 [patent_app_country] => US [patent_app_date] => 1995-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11652 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/479/05479115.pdf [firstpage_image] =>[orig_patent_app_number] => 388433 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/388433
Signal processing device and level converter circuit Feb 13, 1995 Issued
Menu