Andrew Sanders

Array ( [id] => 2852127 [patent_doc_number] => 05111080 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-05 [patent_title] => 'Complementary signal transmission circuit with impedance matching circuitry' [patent_app_type] => 1 [patent_app_number] => 7/614071 [patent_app_country] => US [patent_app_date] => 1990-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 7947 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/111/05111080.pdf [firstpage_image] =>[orig_patent_app_number] => 614071 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2818475 [patent_doc_number] => 05122693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-16 [patent_title] => 'Clock system implementing divided power supply wiring' [patent_app_type] => 1 [patent_app_number] => 7/613187 [patent_app_country] => US [patent_app_date] => 1990-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12166 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/122/05122693.pdf [firstpage_image] =>[orig_patent_app_number] => 613187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2822590 [patent_doc_number] => 05081371 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-14 [patent_title] => 'Integrated charge pump circuit with back bias voltage reduction' [patent_app_type] => 1 [patent_app_number] => 7/610191 [patent_app_country] => US [patent_app_date] => 1990-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3026 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/081/05081371.pdf [firstpage_image] =>[orig_patent_app_number] => 610191 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2780684 [patent_doc_number] => 05151622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-29 [patent_title] => 'CMOS logic circuit with output coupled to multiple feedback paths and associated method' [patent_app_type] => 1 [patent_app_number] => 7/609836 [patent_app_country] => US [patent_app_date] => 1990-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3210 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/151/05151622.pdf [firstpage_image] =>[orig_patent_app_number] => 609836 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2778931 [patent_doc_number] => 05132576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-21 [patent_title] => 'Sense amplifier having load device providing improved access time' [patent_app_type] => 1 [patent_app_number] => 7/609205 [patent_app_country] => US [patent_app_date] => 1990-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1548 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/132/05132576.pdf [firstpage_image] =>[orig_patent_app_number] => 609205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2897006 [patent_doc_number] => 05270586 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-12-14 [patent_title] => 'Controllable delay logic circuit for providing variable delay time' [patent_app_type] => 1 [patent_app_number] => 7/766531 [patent_app_country] => US [patent_app_date] => 1990-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6044 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/270/05270586.pdf [firstpage_image] =>[orig_patent_app_number] => 766531 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2737661 [patent_doc_number] => 05051622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-24 [patent_title] => 'Power-on strap inputs' [patent_app_type] => 1 [patent_app_number] => 7/607206 [patent_app_country] => US [patent_app_date] => 1990-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2118 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/051/05051622.pdf [firstpage_image] =>[orig_patent_app_number] => 607206 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2856747 [patent_doc_number] => 05089725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-02-18 [patent_title] => 'Self-referenced current switch logic circuit with a push-pull output buffer' [patent_app_type] => 1 [patent_app_number] => 7/604842 [patent_app_country] => US [patent_app_date] => 1990-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7888 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/089/05089725.pdf [firstpage_image] =>[orig_patent_app_number] => 604842 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2881090 [patent_doc_number] => 05159216 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-27 [patent_title] => 'Precision tristate output driver circuit having a voltage clamping feature' [patent_app_type] => 1 [patent_app_number] => 7/603338 [patent_app_country] => US [patent_app_date] => 1990-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5141 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/159/05159216.pdf [firstpage_image] =>[orig_patent_app_number] => 603338 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2808994 [patent_doc_number] => 05115148 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-05-19 [patent_title] => 'Interface between two electrical circuits operated at different operating voltages' [patent_app_type] => 1 [patent_app_number] => 7/600668 [patent_app_country] => US [patent_app_date] => 1990-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1494 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/115/05115148.pdf [firstpage_image] =>[orig_patent_app_number] => 600668 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2842728 [patent_doc_number] => 05160859 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-11-03 [patent_title] => 'Synchronous internal clock distribution' [patent_app_type] => 1 [patent_app_number] => 7/601154 [patent_app_country] => US [patent_app_date] => 1990-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1214 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/160/05160859.pdf [firstpage_image] =>[orig_patent_app_number] => 601154 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2818136 [patent_doc_number] => 05122675 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-16 [patent_title] => 'Digital line lock circuit with noise immunity' [patent_app_type] => 1 [patent_app_number] => 7/596850 [patent_app_country] => US [patent_app_date] => 1990-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2973 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/122/05122675.pdf [firstpage_image] =>[orig_patent_app_number] => 596850 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2863702 [patent_doc_number] => 05149993 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-09-22 [patent_title] => 'Circuit arrangement of semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 7/599595 [patent_app_country] => US [patent_app_date] => 1990-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 35 [patent_no_of_words] => 6905 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/149/05149993.pdf [firstpage_image] =>[orig_patent_app_number] => 599595 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2795255 [patent_doc_number] => 05103119 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-07 [patent_title] => 'TTL-level BiCMOS driver' [patent_app_type] => 1 [patent_app_number] => 7/594828 [patent_app_country] => US [patent_app_date] => 1990-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1672 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/103/05103119.pdf [firstpage_image] =>[orig_patent_app_number] => 594828 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2818267 [patent_doc_number] => 05122682 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-16 [patent_title] => 'Source-coupled FET-logic-type logic circuit' [patent_app_type] => 1 [patent_app_number] => 7/593041 [patent_app_country] => US [patent_app_date] => 1990-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 6278 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 699 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/122/05122682.pdf [firstpage_image] =>[orig_patent_app_number] => 593041 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2865198 [patent_doc_number] => 05083046 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-21 [patent_title] => 'Source-coupled FET logic type output circuit' [patent_app_type] => 1 [patent_app_number] => 7/593043 [patent_app_country] => US [patent_app_date] => 1990-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3636 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/083/05083046.pdf [firstpage_image] =>[orig_patent_app_number] => 593043 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3003052 [patent_doc_number] => 05359233 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-25 [patent_title] => 'Reset monitor for detection of power failure and external reset' [patent_app_type] => 1 [patent_app_number] => 7/589937 [patent_app_country] => US [patent_app_date] => 1990-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 7589 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/359/05359233.pdf [firstpage_image] =>[orig_patent_app_number] => 589937 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2710428 [patent_doc_number] => 05068551 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-11-26 [patent_title] => 'Apparatus and method for translating ECL signals to CMOS signals' [patent_app_type] => 1 [patent_app_number] => 7/586068 [patent_app_country] => US [patent_app_date] => 1990-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4007 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/068/05068551.pdf [firstpage_image] =>[orig_patent_app_number] => 586068 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 2822707 [patent_doc_number] => 05081377 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-01-14 [patent_title] => 'Latch circuit with reduced metastability' [patent_app_type] => 1 [patent_app_number] => 7/586127 [patent_app_country] => US [patent_app_date] => 1990-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2438 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/081/05081377.pdf [firstpage_image] =>[orig_patent_app_number] => 586127 [rel_patent_id] =>[rel_patent_doc_number] =>)