Search

Andrew Sanders

Examiner (ID: 1323)

Most Active Art Unit
2509
Art Unit(s)
2509, 2504
Total Applications
463
Issued Applications
431
Pending Applications
2
Abandoned Applications
30

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2680521 [patent_doc_number] => 05048016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-10 [patent_title] => 'Circuit configuration for increasing the output voltage of an electronic switching stage' [patent_app_type] => 1 [patent_app_number] => 7/579046 [patent_app_country] => US [patent_app_date] => 1990-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1430 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/048/05048016.pdf [firstpage_image] =>[orig_patent_app_number] => 579046 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/579046
Circuit configuration for increasing the output voltage of an electronic switching stage Sep 6, 1990 Issued
Array ( [id] => 2777864 [patent_doc_number] => 05075580 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-24 [patent_title] => 'Circuit for converting an ECL signal into a CMOS signal' [patent_app_type] => 1 [patent_app_number] => 7/578744 [patent_app_country] => US [patent_app_date] => 1990-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1635 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 449 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/075/05075580.pdf [firstpage_image] =>[orig_patent_app_number] => 578744 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/578744
Circuit for converting an ECL signal into a CMOS signal Sep 5, 1990 Issued
Array ( [id] => 2818402 [patent_doc_number] => 05122689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-06-16 [patent_title] => 'CMOS to ECL/CML level converter' [patent_app_type] => 1 [patent_app_number] => 7/577472 [patent_app_country] => US [patent_app_date] => 1990-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 4274 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/122/05122689.pdf [firstpage_image] =>[orig_patent_app_number] => 577472 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/577472
CMOS to ECL/CML level converter Sep 3, 1990 Issued
Array ( [id] => 2882379 [patent_doc_number] => 05185539 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1993-02-09 [patent_title] => 'Programmable logic device address buffer/multiplexer/driver' [patent_app_type] => 1 [patent_app_number] => 7/576565 [patent_app_country] => US [patent_app_date] => 1990-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1338 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/185/05185539.pdf [firstpage_image] =>[orig_patent_app_number] => 576565 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/576565
Programmable logic device address buffer/multiplexer/driver Aug 30, 1990 Issued
07/574178 BICMOS LOGIC CIRCUIT WITH A CML OUTPUT Aug 28, 1990 Abandoned
07/569359 SELF LATCHING INPUT BUFFER Aug 16, 1990 Abandoned
Array ( [id] => 2728041 [patent_doc_number] => 05057703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-10-15 [patent_title] => 'Working/standby clock pulse supply for digital systems' [patent_app_type] => 1 [patent_app_number] => 7/567973 [patent_app_country] => US [patent_app_date] => 1990-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2474 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/057/05057703.pdf [firstpage_image] =>[orig_patent_app_number] => 567973 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/567973
Working/standby clock pulse supply for digital systems Aug 14, 1990 Issued
Array ( [id] => 2854134 [patent_doc_number] => 05105107 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-04-14 [patent_title] => 'High speed CMOS differential interface circuits' [patent_app_type] => 1 [patent_app_number] => 7/560989 [patent_app_country] => US [patent_app_date] => 1990-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 1266 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/105/05105107.pdf [firstpage_image] =>[orig_patent_app_number] => 560989 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/560989
High speed CMOS differential interface circuits Jul 31, 1990 Issued
Array ( [id] => 2747925 [patent_doc_number] => 05023479 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-06-11 [patent_title] => 'Low power output gate' [patent_app_type] => 1 [patent_app_number] => 7/560920 [patent_app_country] => US [patent_app_date] => 1990-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2114 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/023/05023479.pdf [firstpage_image] =>[orig_patent_app_number] => 560920 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/560920
Low power output gate Jul 30, 1990 Issued
Array ( [id] => 2778701 [patent_doc_number] => 05132564 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-07-21 [patent_title] => 'Bus driver circuit with low on-chip dissipation and/or pre-biasing of output terminal during live insertion' [patent_app_type] => 1 [patent_app_number] => 7/558935 [patent_app_country] => US [patent_app_date] => 1990-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 6098 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/132/05132564.pdf [firstpage_image] =>[orig_patent_app_number] => 558935 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/558935
Bus driver circuit with low on-chip dissipation and/or pre-biasing of output terminal during live insertion Jul 26, 1990 Issued
Array ( [id] => 2713898 [patent_doc_number] => 05017807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-05-21 [patent_title] => 'Output buffer having capacitive drive shunt for reduced noise' [patent_app_type] => 1 [patent_app_number] => 7/549519 [patent_app_country] => US [patent_app_date] => 1990-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2157 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/017/05017807.pdf [firstpage_image] =>[orig_patent_app_number] => 549519 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/549519
Output buffer having capacitive drive shunt for reduced noise Jul 4, 1990 Issued
Array ( [id] => 2881003 [patent_doc_number] => 05159212 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-10-27 [patent_title] => 'Protection device for a digital signal transmission system' [patent_app_type] => 1 [patent_app_number] => 7/545728 [patent_app_country] => US [patent_app_date] => 1990-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2356 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/159/05159212.pdf [firstpage_image] =>[orig_patent_app_number] => 545728 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/545728
Protection device for a digital signal transmission system Jun 28, 1990 Issued
Array ( [id] => 2674526 [patent_doc_number] => 05034632 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-23 [patent_title] => 'High speed TTL buffer circuit and line driver' [patent_app_type] => 1 [patent_app_number] => 7/540641 [patent_app_country] => US [patent_app_date] => 1990-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 7582 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/034/05034632.pdf [firstpage_image] =>[orig_patent_app_number] => 540641 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/540641
High speed TTL buffer circuit and line driver Jun 18, 1990 Issued
Array ( [id] => 2691432 [patent_doc_number] => 05049765 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-17 [patent_title] => 'BiCMOS noninverting buffer and logic gates' [patent_app_type] => 1 [patent_app_number] => 7/540342 [patent_app_country] => US [patent_app_date] => 1990-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4823 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/049/05049765.pdf [firstpage_image] =>[orig_patent_app_number] => 540342 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/540342
BiCMOS noninverting buffer and logic gates Jun 18, 1990 Issued
Array ( [id] => 2747261 [patent_doc_number] => 05028817 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-02 [patent_title] => 'Tristable output buffer with state transition control' [patent_app_type] => 1 [patent_app_number] => 7/537578 [patent_app_country] => US [patent_app_date] => 1990-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1323 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/028/05028817.pdf [firstpage_image] =>[orig_patent_app_number] => 537578 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/537578
Tristable output buffer with state transition control Jun 13, 1990 Issued
Array ( [id] => 2710826 [patent_doc_number] => 05001371 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-03-19 [patent_title] => 'Meta-stable free flipflop' [patent_app_type] => 1 [patent_app_number] => 7/535618 [patent_app_country] => US [patent_app_date] => 1990-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2140 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/001/05001371.pdf [firstpage_image] =>[orig_patent_app_number] => 535618 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/535618
Meta-stable free flipflop Jun 10, 1990 Issued
Array ( [id] => 2747298 [patent_doc_number] => 05028819 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-02 [patent_title] => 'High CMOS open-drain output buffer' [patent_app_type] => 1 [patent_app_number] => 7/535403 [patent_app_country] => US [patent_app_date] => 1990-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2355 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/028/05028819.pdf [firstpage_image] =>[orig_patent_app_number] => 535403 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/535403
High CMOS open-drain output buffer Jun 7, 1990 Issued
Array ( [id] => 2736805 [patent_doc_number] => 05032741 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-16 [patent_title] => 'CDCFL logic circuits having shared loads' [patent_app_type] => 1 [patent_app_number] => 7/532723 [patent_app_country] => US [patent_app_date] => 1990-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2743 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/032/05032741.pdf [firstpage_image] =>[orig_patent_app_number] => 532723 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/532723
CDCFL logic circuits having shared loads Jun 3, 1990 Issued
Array ( [id] => 2674596 [patent_doc_number] => 05034636 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-23 [patent_title] => 'Sense amplifier with an integral logic function' [patent_app_type] => 1 [patent_app_number] => 7/534562 [patent_app_country] => US [patent_app_date] => 1990-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3999 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/034/05034636.pdf [firstpage_image] =>[orig_patent_app_number] => 534562 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/534562
Sense amplifier with an integral logic function Jun 3, 1990 Issued
Array ( [id] => 2752876 [patent_doc_number] => 05038057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-06 [patent_title] => 'ECL to CMOS logic translator' [patent_app_type] => 1 [patent_app_number] => 7/529833 [patent_app_country] => US [patent_app_date] => 1990-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2356 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/038/05038057.pdf [firstpage_image] =>[orig_patent_app_number] => 529833 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/529833
ECL to CMOS logic translator May 28, 1990 Issued
Menu