
Andrew Sanders
Examiner (ID: 4354)
| Most Active Art Unit | 2509 |
| Art Unit(s) | 2509, 2504 |
| Total Applications | 463 |
| Issued Applications | 431 |
| Pending Applications | 2 |
| Abandoned Applications | 30 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3502470
[patent_doc_number] => 05532624
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-02
[patent_title] => 'High-speed and accurate sample and hold circuits'
[patent_app_type] => 1
[patent_app_number] => 8/381627
[patent_app_country] => US
[patent_app_date] => 1995-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1642
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/532/05532624.pdf
[firstpage_image] =>[orig_patent_app_number] => 381627
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/381627 | High-speed and accurate sample and hold circuits | Jan 30, 1995 | Issued |
Array
(
[id] => 3512525
[patent_doc_number] => 05570043
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-29
[patent_title] => 'Overvoltage tolerant intergrated circuit output buffer'
[patent_app_type] => 1
[patent_app_number] => 8/381125
[patent_app_country] => US
[patent_app_date] => 1995-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 7190
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[pdf_file] => patents/05/570/05570043.pdf
[firstpage_image] =>[orig_patent_app_number] => 381125
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/381125 | Overvoltage tolerant intergrated circuit output buffer | Jan 30, 1995 | Issued |
Array
(
[id] => 3586910
[patent_doc_number] => 05498981
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-12
[patent_title] => 'Ready signal control apparatus capable of automatically deactivating ready signal'
[patent_app_type] => 1
[patent_app_number] => 8/381327
[patent_app_country] => US
[patent_app_date] => 1995-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 2707
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[pdf_file] => patents/05/498/05498981.pdf
[firstpage_image] =>[orig_patent_app_number] => 381327
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/381327 | Ready signal control apparatus capable of automatically deactivating ready signal | Jan 30, 1995 | Issued |
Array
(
[id] => 3617805
[patent_doc_number] => 05534793
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-09
[patent_title] => 'Parallel antifuse routing scheme (PARS) circuit and method for field programmable gate arrays'
[patent_app_type] => 1
[patent_app_number] => 8/378036
[patent_app_country] => US
[patent_app_date] => 1995-01-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 3087
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 42
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/534/05534793.pdf
[firstpage_image] =>[orig_patent_app_number] => 378036
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/378036 | Parallel antifuse routing scheme (PARS) circuit and method for field programmable gate arrays | Jan 23, 1995 | Issued |
Array
(
[id] => 3424557
[patent_doc_number] => 05479117
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-26
[patent_title] => 'Hybrid data processing system including pulsed-power-supply CMOS circuits'
[patent_app_type] => 1
[patent_app_number] => 8/371254
[patent_app_country] => US
[patent_app_date] => 1995-01-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 4242
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/479/05479117.pdf
[firstpage_image] =>[orig_patent_app_number] => 371254
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/371254 | Hybrid data processing system including pulsed-power-supply CMOS circuits | Jan 10, 1995 | Issued |
Array
(
[id] => 3499940
[patent_doc_number] => 05508637
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-16
[patent_title] => 'Logic module for a field programmable gate array'
[patent_app_type] => 1
[patent_app_number] => 8/368931
[patent_app_country] => US
[patent_app_date] => 1995-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 3530
[patent_no_of_claims] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/508/05508637.pdf
[firstpage_image] =>[orig_patent_app_number] => 368931
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/368931 | Logic module for a field programmable gate array | Jan 4, 1995 | Issued |
Array
(
[id] => 3608048
[patent_doc_number] => 05578943
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-26
[patent_title] => 'Signal transmitter and apparatus incorporating same'
[patent_app_type] => 1
[patent_app_number] => 8/368945
[patent_app_country] => US
[patent_app_date] => 1995-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2404
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/578/05578943.pdf
[firstpage_image] =>[orig_patent_app_number] => 368945
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/368945 | Signal transmitter and apparatus incorporating same | Jan 4, 1995 | Issued |
Array
(
[id] => 3421334
[patent_doc_number] => 05453708
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-09-26
[patent_title] => 'Clocking scheme for latching of a domino output'
[patent_app_type] => 1
[patent_app_number] => 8/368335
[patent_app_country] => US
[patent_app_date] => 1995-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 4361
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 287
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/453/05453708.pdf
[firstpage_image] =>[orig_patent_app_number] => 368335
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/368335 | Clocking scheme for latching of a domino output | Jan 3, 1995 | Issued |
Array
(
[id] => 3577077
[patent_doc_number] => 05539337
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-23
[patent_title] => 'Clock noise filter for integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/367842
[patent_app_country] => US
[patent_app_date] => 1994-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 1930
[patent_no_of_claims] => 47
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/539/05539337.pdf
[firstpage_image] =>[orig_patent_app_number] => 367842
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/367842 | Clock noise filter for integrated circuits | Dec 29, 1994 | Issued |
Array
(
[id] => 3604218
[patent_doc_number] => 05559459
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-24
[patent_title] => 'Clock signal generation arrangement including digital noise reduction circuit for reducing noise in a digital clocking signal'
[patent_app_type] => 1
[patent_app_number] => 8/366414
[patent_app_country] => US
[patent_app_date] => 1994-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 7434
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/559/05559459.pdf
[firstpage_image] =>[orig_patent_app_number] => 366414
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/366414 | Clock signal generation arrangement including digital noise reduction circuit for reducing noise in a digital clocking signal | Dec 28, 1994 | Issued |
Array
(
[id] => 3617873
[patent_doc_number] => 05534797
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-09
[patent_title] => 'Compact and fast row driver/decoder for semiconductor memory'
[patent_app_type] => 1
[patent_app_number] => 8/363046
[patent_app_country] => US
[patent_app_date] => 1994-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 3055
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/534/05534797.pdf
[firstpage_image] =>[orig_patent_app_number] => 363046
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/363046 | Compact and fast row driver/decoder for semiconductor memory | Dec 22, 1994 | Issued |
Array
(
[id] => 3619809
[patent_doc_number] => 05510733
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-23
[patent_title] => 'High speed circuit with CMOS and bipolar logic stages'
[patent_app_type] => 1
[patent_app_number] => 8/363729
[patent_app_country] => US
[patent_app_date] => 1994-12-23
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/510/05510733.pdf
[firstpage_image] =>[orig_patent_app_number] => 363729
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/363729 | High speed circuit with CMOS and bipolar logic stages | Dec 22, 1994 | Issued |
Array
(
[id] => 3543134
[patent_doc_number] => 05495189
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-27
[patent_title] => 'Non-overlap signal generation circuit'
[patent_app_type] => 1
[patent_app_number] => 8/362315
[patent_app_country] => US
[patent_app_date] => 1994-12-22
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[pdf_file] => patents/05/495/05495189.pdf
[firstpage_image] =>[orig_patent_app_number] => 362315
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/362315 | Non-overlap signal generation circuit | Dec 21, 1994 | Issued |
Array
(
[id] => 3497758
[patent_doc_number] => 05537060
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-16
[patent_title] => 'Output buffer circuit for memory device'
[patent_app_type] => 1
[patent_app_number] => 8/362301
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[pdf_file] => patents/05/537/05537060.pdf
[firstpage_image] =>[orig_patent_app_number] => 362301
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/362301 | Output buffer circuit for memory device | Dec 21, 1994 | Issued |
Array
(
[id] => 3597835
[patent_doc_number] => 05521537
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-28
[patent_title] => 'Bus interface logic integrated circuit'
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[pdf_file] => patents/05/521/05521537.pdf
[firstpage_image] =>[orig_patent_app_number] => 363645
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/363645 | Bus interface logic integrated circuit | Dec 21, 1994 | Issued |
Array
(
[id] => 3510635
[patent_doc_number] => 05514983
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-07
[patent_title] => 'CMOS full duplex transmission-reception circuit'
[patent_app_type] => 1
[patent_app_number] => 8/360325
[patent_app_country] => US
[patent_app_date] => 1994-12-21
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[pdf_file] => patents/05/514/05514983.pdf
[firstpage_image] =>[orig_patent_app_number] => 360325
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/360325 | CMOS full duplex transmission-reception circuit | Dec 20, 1994 | Issued |
Array
(
[id] => 3593875
[patent_doc_number] => 05517130
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-14
[patent_title] => 'Method and structure for reducing noise in output buffer circuits'
[patent_app_type] => 1
[patent_app_number] => 8/359902
[patent_app_country] => US
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[pdf_file] => patents/05/517/05517130.pdf
[firstpage_image] =>[orig_patent_app_number] => 359902
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/359902 | Method and structure for reducing noise in output buffer circuits | Dec 19, 1994 | Issued |
Array
(
[id] => 3462773
[patent_doc_number] => 05473263
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-05
[patent_title] => 'Negative feedback to reduce voltage oscillation in CMOS output buffers'
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[patent_app_number] => 8/359235
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[pdf_file] => patents/05/473/05473263.pdf
[firstpage_image] =>[orig_patent_app_number] => 359235
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/359235 | Negative feedback to reduce voltage oscillation in CMOS output buffers | Dec 18, 1994 | Issued |
Array
(
[id] => 3569565
[patent_doc_number] => 05483181
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[patent_kind] => NA
[patent_issue_date] => 1996-01-09
[patent_title] => 'Dynamic logic circuit with reduced charge leakage'
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[pdf_file] => patents/05/483/05483181.pdf
[firstpage_image] =>[orig_patent_app_number] => 357033
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/357033 | Dynamic logic circuit with reduced charge leakage | Dec 15, 1994 | Issued |
Array
(
[id] => 3655415
[patent_doc_number] => 05606270
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-25
[patent_title] => 'Dynamic clocked inverter latch with reduced charge leakage'
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[patent_app_number] => 8/357607
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[pdf_file] => patents/05/606/05606270.pdf
[firstpage_image] =>[orig_patent_app_number] => 357607
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/357607 | Dynamic clocked inverter latch with reduced charge leakage | Dec 15, 1994 | Issued |