
Andrew Sanders
Examiner (ID: 4354)
| Most Active Art Unit | 2509 |
| Art Unit(s) | 2509, 2504 |
| Total Applications | 463 |
| Issued Applications | 431 |
| Pending Applications | 2 |
| Abandoned Applications | 30 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3502401
[patent_doc_number] => 05532619
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-02
[patent_title] => 'Precision level shifter w/current mirror'
[patent_app_type] => 1
[patent_app_number] => 8/356816
[patent_app_country] => US
[patent_app_date] => 1994-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2657
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/532/05532619.pdf
[firstpage_image] =>[orig_patent_app_number] => 356816
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/356816 | Precision level shifter w/current mirror | Dec 14, 1994 | Issued |
Array
(
[id] => 3467101
[patent_doc_number] => 05469082
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-21
[patent_title] => 'Peripheral component interfacing system with bus voltage/logic supply comparison means'
[patent_app_type] => 1
[patent_app_number] => 8/352331
[patent_app_country] => US
[patent_app_date] => 1994-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2908
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/469/05469082.pdf
[firstpage_image] =>[orig_patent_app_number] => 352331
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/352331 | Peripheral component interfacing system with bus voltage/logic supply comparison means | Dec 7, 1994 | Issued |
Array
(
[id] => 3594426
[patent_doc_number] => 05497108
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-05
[patent_title] => 'BICMOS repeater circuit for a programmable logic device'
[patent_app_type] => 1
[patent_app_number] => 8/352402
[patent_app_country] => US
[patent_app_date] => 1994-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4149
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/497/05497108.pdf
[firstpage_image] =>[orig_patent_app_number] => 352402
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/352402 | BICMOS repeater circuit for a programmable logic device | Dec 7, 1994 | Issued |
Array
(
[id] => 3557899
[patent_doc_number] => 05493233
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-20
[patent_title] => 'MOSFET circuit apparatus with avalanche breakdown prevention means'
[patent_app_type] => 1
[patent_app_number] => 8/353397
[patent_app_country] => US
[patent_app_date] => 1994-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5241
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/493/05493233.pdf
[firstpage_image] =>[orig_patent_app_number] => 353397
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/353397 | MOSFET circuit apparatus with avalanche breakdown prevention means | Dec 1, 1994 | Issued |
Array
(
[id] => 3485672
[patent_doc_number] => 05457411
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-10
[patent_title] => 'Trinary logic input gate'
[patent_app_type] => 1
[patent_app_number] => 8/348633
[patent_app_country] => US
[patent_app_date] => 1994-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 7356
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/457/05457411.pdf
[firstpage_image] =>[orig_patent_app_number] => 348633
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/348633 | Trinary logic input gate | Dec 1, 1994 | Issued |
Array
(
[id] => 3448028
[patent_doc_number] => 05467028
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-14
[patent_title] => 'Semiconductor integrated circuit with plural use of a terminal'
[patent_app_type] => 1
[patent_app_number] => 8/337423
[patent_app_country] => US
[patent_app_date] => 1994-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3242
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/467/05467028.pdf
[firstpage_image] =>[orig_patent_app_number] => 337423
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/337423 | Semiconductor integrated circuit with plural use of a terminal | Nov 7, 1994 | Issued |
Array
(
[id] => 3669896
[patent_doc_number] => 05598110
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-28
[patent_title] => 'Detector circuit for use with tri-state logic devices'
[patent_app_type] => 1
[patent_app_number] => 8/332834
[patent_app_country] => US
[patent_app_date] => 1994-11-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 24
[patent_no_of_words] => 3704
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 310
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/598/05598110.pdf
[firstpage_image] =>[orig_patent_app_number] => 332834
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/332834 | Detector circuit for use with tri-state logic devices | Oct 31, 1994 | Issued |
Array
(
[id] => 3576991
[patent_doc_number] => 05539332
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-23
[patent_title] => 'Adder circuits and magnitude comparator'
[patent_app_type] => 1
[patent_app_number] => 8/331436
[patent_app_country] => US
[patent_app_date] => 1994-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2021
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 139
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/539/05539332.pdf
[firstpage_image] =>[orig_patent_app_number] => 331436
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/331436 | Adder circuits and magnitude comparator | Oct 30, 1994 | Issued |
Array
(
[id] => 3494892
[patent_doc_number] => 05471161
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-28
[patent_title] => 'Circuit for calculating the minimum value'
[patent_app_type] => 1
[patent_app_number] => 8/322407
[patent_app_country] => US
[patent_app_date] => 1994-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 518
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/471/05471161.pdf
[firstpage_image] =>[orig_patent_app_number] => 322407
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/322407 | Circuit for calculating the minimum value | Oct 11, 1994 | Issued |
Array
(
[id] => 3448059
[patent_doc_number] => 05467030
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-14
[patent_title] => 'Circuit for calculating a maximum value'
[patent_app_type] => 1
[patent_app_number] => 8/322408
[patent_app_country] => US
[patent_app_date] => 1994-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 528
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/467/05467030.pdf
[firstpage_image] =>[orig_patent_app_number] => 322408
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/322408 | Circuit for calculating a maximum value | Oct 11, 1994 | Issued |
Array
(
[id] => 3418135
[patent_doc_number] => 05444397
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-22
[patent_title] => 'All-CMOS high-impedance output buffer for a bus driven by multiple power-supply voltages'
[patent_app_type] => 1
[patent_app_number] => 8/318238
[patent_app_country] => US
[patent_app_date] => 1994-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 5919
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/444/05444397.pdf
[firstpage_image] =>[orig_patent_app_number] => 318238
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/318238 | All-CMOS high-impedance output buffer for a bus driven by multiple power-supply voltages | Oct 4, 1994 | Issued |
Array
(
[id] => 3673357
[patent_doc_number] => 05600261
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-04
[patent_title] => 'Output enable access for an output buffer'
[patent_app_type] => 1
[patent_app_number] => 8/318146
[patent_app_country] => US
[patent_app_date] => 1994-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 9775
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/600/05600261.pdf
[firstpage_image] =>[orig_patent_app_number] => 318146
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/318146 | Output enable access for an output buffer | Oct 4, 1994 | Issued |
Array
(
[id] => 3584834
[patent_doc_number] => 05491431
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-13
[patent_title] => 'Logic module core cell for gate arrays'
[patent_app_type] => 1
[patent_app_number] => 8/318322
[patent_app_country] => US
[patent_app_date] => 1994-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 2497
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/491/05491431.pdf
[firstpage_image] =>[orig_patent_app_number] => 318322
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/318322 | Logic module core cell for gate arrays | Oct 4, 1994 | Issued |
Array
(
[id] => 3414250
[patent_doc_number] => 05438284
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-01
[patent_title] => 'Basic logic circuit having multi-emitter transistor'
[patent_app_type] => 1
[patent_app_number] => 8/317738
[patent_app_country] => US
[patent_app_date] => 1994-10-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 22
[patent_no_of_words] => 5933
[patent_no_of_claims] => 19
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[patent_words_short_claim] => 264
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/438/05438284.pdf
[firstpage_image] =>[orig_patent_app_number] => 317738
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/317738 | Basic logic circuit having multi-emitter transistor | Oct 3, 1994 | Issued |
Array
(
[id] => 3593988
[patent_doc_number] => 05517138
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-14
[patent_title] => 'Dual row selection using multiplexed tri-level decoder'
[patent_app_type] => 1
[patent_app_number] => 8/316546
[patent_app_country] => US
[patent_app_date] => 1994-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/517/05517138.pdf
[firstpage_image] =>[orig_patent_app_number] => 316546
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/316546 | Dual row selection using multiplexed tri-level decoder | Sep 29, 1994 | Issued |
Array
(
[id] => 3454262
[patent_doc_number] => 05424654
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-06-13
[patent_title] => 'Programmable macrocell circuit'
[patent_app_type] => 1
[patent_app_number] => 8/310437
[patent_app_country] => US
[patent_app_date] => 1994-09-22
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 2563
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/424/05424654.pdf
[firstpage_image] =>[orig_patent_app_number] => 310437
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/310437 | Programmable macrocell circuit | Sep 21, 1994 | Issued |
Array
(
[id] => 3448073
[patent_doc_number] => 05467031
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-14
[patent_title] => '3.3 volt CMOS tri-state driver circuit capable of driving common 5 volt line'
[patent_app_type] => 1
[patent_app_number] => 8/310941
[patent_app_country] => US
[patent_app_date] => 1994-09-22
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/467/05467031.pdf
[firstpage_image] =>[orig_patent_app_number] => 310941
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/310941 | 3.3 volt CMOS tri-state driver circuit capable of driving common 5 volt line | Sep 21, 1994 | Issued |
Array
(
[id] => 3418118
[patent_doc_number] => 05444396
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-22
[patent_title] => 'Level shifting circuit'
[patent_app_type] => 1
[patent_app_number] => 8/309632
[patent_app_country] => US
[patent_app_date] => 1994-09-21
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[pdf_file] => patents/05/444/05444396.pdf
[firstpage_image] =>[orig_patent_app_number] => 309632
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/309632 | Level shifting circuit | Sep 20, 1994 | Issued |
Array
(
[id] => 3467042
[patent_doc_number] => 05469079
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-11-21
[patent_title] => 'Flip-flop for use in LSSD gate arrays'
[patent_app_type] => 1
[patent_app_number] => 8/305238
[patent_app_country] => US
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[pdf_file] => patents/05/469/05469079.pdf
[firstpage_image] =>[orig_patent_app_number] => 305238
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/305238 | Flip-flop for use in LSSD gate arrays | Sep 12, 1994 | Issued |
Array
(
[id] => 3462802
[patent_doc_number] => 05473265
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-12-05
[patent_title] => 'Circuit configuration for the generation of a line terminating impedance'
[patent_app_type] => 1
[patent_app_number] => 8/300433
[patent_app_country] => US
[patent_app_date] => 1994-09-02
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/473/05473265.pdf
[firstpage_image] =>[orig_patent_app_number] => 300433
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/300433 | Circuit configuration for the generation of a line terminating impedance | Sep 1, 1994 | Issued |