Andrew Sanders

Array ( [id] => 3424536 [patent_doc_number] => 05444821 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-22 [patent_title] => 'Artificial neuron element with electrically programmable synaptic weight for neural networks' [patent_app_type] => 1 [patent_app_number] => 8/150460 [patent_app_country] => US [patent_app_date] => 1993-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2994 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/444/05444821.pdf [firstpage_image] =>[orig_patent_app_number] => 150460 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3495578 [patent_doc_number] => 05440244 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-08 [patent_title] => 'Method and apparatus for controlling a mixed voltage interface in a multivoltage system' [patent_app_type] => 1 [patent_app_number] => 8/149061 [patent_app_country] => US [patent_app_date] => 1993-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 16057 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/440/05440244.pdf [firstpage_image] =>[orig_patent_app_number] => 149061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3463947 [patent_doc_number] => 05382844 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-01-17 [patent_title] => 'Logic circuit for asynchronous circuits with n-channel logic block and p-channel logic block inverse thereto' [patent_app_type] => 1 [patent_app_number] => 8/146061 [patent_app_country] => US [patent_app_date] => 1993-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3282 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/382/05382844.pdf [firstpage_image] =>[orig_patent_app_number] => 146061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3431406 [patent_doc_number] => 05404049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Fuse blow circuit' [patent_app_type] => 1 [patent_app_number] => 8/146253 [patent_app_country] => US [patent_app_date] => 1993-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1543 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404049.pdf [firstpage_image] =>[orig_patent_app_number] => 146253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3545176 [patent_doc_number] => 05481208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-02 [patent_title] => 'Piecewisely-controlled tri-state output buffer' [patent_app_type] => 1 [patent_app_number] => 8/144576 [patent_app_country] => US [patent_app_date] => 1993-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2967 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/481/05481208.pdf [firstpage_image] =>[orig_patent_app_number] => 144576 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3448045 [patent_doc_number] => 05467029 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-14 [patent_title] => 'OR array architecture for a programmable logic device' [patent_app_type] => 1 [patent_app_number] => 8/144663 [patent_app_country] => US [patent_app_date] => 1993-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2667 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/467/05467029.pdf [firstpage_image] =>[orig_patent_app_number] => 144663 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3488424 [patent_doc_number] => 05446407 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-29 [patent_title] => 'Trimming circuit' [patent_app_type] => 1 [patent_app_number] => 8/141974 [patent_app_country] => US [patent_app_date] => 1993-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5438 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/446/05446407.pdf [firstpage_image] =>[orig_patent_app_number] => 141974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3447544 [patent_doc_number] => 05397938 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-14 [patent_title] => 'Current mode logic switching stage' [patent_app_type] => 1 [patent_app_number] => 8/144574 [patent_app_country] => US [patent_app_date] => 1993-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2863 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/397/05397938.pdf [firstpage_image] =>[orig_patent_app_number] => 144574 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3107926 [patent_doc_number] => 05448185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Programmable dedicated FPGA functional blocks for multiple wide-input functions' [patent_app_type] => 1 [patent_app_number] => 8/144452 [patent_app_country] => US [patent_app_date] => 1993-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2715 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/448/05448185.pdf [firstpage_image] =>[orig_patent_app_number] => 144452 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3526641 [patent_doc_number] => 05489860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-02-06 [patent_title] => 'Semiconductor circuit having improved layout pattern' [patent_app_type] => 1 [patent_app_number] => 8/138081 [patent_app_country] => US [patent_app_date] => 1993-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 21 [patent_no_of_words] => 5118 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/489/05489860.pdf [firstpage_image] =>[orig_patent_app_number] => 138081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3458388 [patent_doc_number] => 05451888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-19 [patent_title] => 'Direct coupled FET logic translator circuit' [patent_app_type] => 1 [patent_app_number] => 8/137774 [patent_app_country] => US [patent_app_date] => 1993-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 21 [patent_no_of_words] => 6263 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/451/05451888.pdf [firstpage_image] =>[orig_patent_app_number] => 137774 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3121035 [patent_doc_number] => 05410266 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'Circuit for conversion of shifted differential ECL voltage levels to CMOS voltage levels with process compensation' [patent_app_type] => 1 [patent_app_number] => 8/138656 [patent_app_country] => US [patent_app_date] => 1993-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1453 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/410/05410266.pdf [firstpage_image] =>[orig_patent_app_number] => 138656 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3077679 [patent_doc_number] => 05365127 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-15 [patent_title] => 'Circuit for conversion from CMOS voltage levels to shifted ECL voltage levels with process compensation' [patent_app_type] => 1 [patent_app_number] => 8/139247 [patent_app_country] => US [patent_app_date] => 1993-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1851 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/365/05365127.pdf [firstpage_image] =>[orig_patent_app_number] => 139247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3561800 [patent_doc_number] => 05500610 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-19 [patent_title] => 'Very high current integrated circuit output buffer with short circuit protection and reduced power bus spikes' [patent_app_type] => 1 [patent_app_number] => 8/134571 [patent_app_country] => US [patent_app_date] => 1993-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 12224 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/500/05500610.pdf [firstpage_image] =>[orig_patent_app_number] => 134571 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3446306 [patent_doc_number] => 05430336 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Emitter coupled logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/132970 [patent_app_country] => US [patent_app_date] => 1993-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6454 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/430/05430336.pdf [firstpage_image] =>[orig_patent_app_number] => 132970 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3116111 [patent_doc_number] => 05414305 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-05-09 [patent_title] => 'Output circuit having capability of keeping logic state of signal sent between logic circuits' [patent_app_type] => 1 [patent_app_number] => 8/132363 [patent_app_country] => US [patent_app_date] => 1993-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 1817 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/414/05414305.pdf [firstpage_image] =>[orig_patent_app_number] => 132363 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3485700 [patent_doc_number] => 05457413 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-10 [patent_title] => 'BiMIS logic circuit' [patent_app_type] => 1 [patent_app_number] => 8/130661 [patent_app_country] => US [patent_app_date] => 1993-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 30 [patent_no_of_words] => 9980 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/457/05457413.pdf [firstpage_image] =>[orig_patent_app_number] => 130661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3484301 [patent_doc_number] => 05399918 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-21 [patent_title] => 'Large fan-in, dynamic, bicmos logic gate' [patent_app_type] => 1 [patent_app_number] => 8/129664 [patent_app_country] => US [patent_app_date] => 1993-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7329 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/399/05399918.pdf [firstpage_image] =>[orig_patent_app_number] => 129664 [rel_patent_id] =>[rel_patent_doc_number] =>)