
Andrew Sanders
Examiner (ID: 3675)
| Most Active Art Unit | 2509 |
| Art Unit(s) | 2504, 2509 |
| Total Applications | 463 |
| Issued Applications | 431 |
| Pending Applications | 2 |
| Abandoned Applications | 30 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3586894
[patent_doc_number] => 05498980
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-03-12
[patent_title] => 'Ternary/binary converter circuit'
[patent_app_type] => 1
[patent_app_number] => 8/126333
[patent_app_country] => US
[patent_app_date] => 1993-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3041
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/498/05498980.pdf
[firstpage_image] =>[orig_patent_app_number] => 126333
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/126333 | Ternary/binary converter circuit | Sep 23, 1993 | Issued |
Array
(
[id] => 3454687
[patent_doc_number] => 05386153
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-31
[patent_title] => 'Buffer with pseudo-ground hysteresis'
[patent_app_type] => 1
[patent_app_number] => 8/126065
[patent_app_country] => US
[patent_app_date] => 1993-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 4809
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 178
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/386/05386153.pdf
[firstpage_image] =>[orig_patent_app_number] => 126065
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/126065 | Buffer with pseudo-ground hysteresis | Sep 22, 1993 | Issued |
Array
(
[id] => 3466429
[patent_doc_number] => 05391941
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-02-21
[patent_title] => 'Decoder circuitry with balanced propagation delay and minimized input capacitance'
[patent_app_type] => 1
[patent_app_number] => 8/126069
[patent_app_country] => US
[patent_app_date] => 1993-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4880
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/391/05391941.pdf
[firstpage_image] =>[orig_patent_app_number] => 126069
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/126069 | Decoder circuitry with balanced propagation delay and minimized input capacitance | Sep 22, 1993 | Issued |
Array
(
[id] => 3454726
[patent_doc_number] => 05386156
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-01-31
[patent_title] => 'Programmable function unit with programmable fast ripple logic'
[patent_app_type] => 1
[patent_app_number] => 8/113154
[patent_app_country] => US
[patent_app_date] => 1993-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 2162
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/386/05386156.pdf
[firstpage_image] =>[orig_patent_app_number] => 113154
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/113154 | Programmable function unit with programmable fast ripple logic | Aug 26, 1993 | Issued |
Array
(
[id] => 3447581
[patent_doc_number] => 05397941
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-14
[patent_title] => 'Interface circuits between powered down devices and a bus'
[patent_app_type] => 1
[patent_app_number] => 8/110168
[patent_app_country] => US
[patent_app_date] => 1993-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 2830
[patent_no_of_claims] => 47
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/397/05397941.pdf
[firstpage_image] =>[orig_patent_app_number] => 110168
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/110168 | Interface circuits between powered down devices and a bus | Aug 19, 1993 | Issued |
Array
(
[id] => 3007176
[patent_doc_number] => 05371423
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-12-06
[patent_title] => 'Tri-state-capable driver circuit'
[patent_app_type] => 1
[patent_app_number] => 8/107960
[patent_app_country] => US
[patent_app_date] => 1993-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3544
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 516
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/371/05371423.pdf
[firstpage_image] =>[orig_patent_app_number] => 107960
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/107960 | Tri-state-capable driver circuit | Aug 16, 1993 | Issued |
Array
(
[id] => 3416341
[patent_doc_number] => 05412259
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-02
[patent_title] => 'Input buffer with level detector circuit'
[patent_app_type] => 1
[patent_app_number] => 8/104654
[patent_app_country] => US
[patent_app_date] => 1993-08-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 3
[patent_no_of_words] => 3285
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 385
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/412/05412259.pdf
[firstpage_image] =>[orig_patent_app_number] => 104654
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/104654 | Input buffer with level detector circuit | Aug 10, 1993 | Issued |
| 08/100228 | FULL DIFFERENTIAL DATA QUALIFICATION CIRCUIT FOR SENSING A LOGIC STATE | Aug 1, 1993 | Pending |
Array
(
[id] => 3111985
[patent_doc_number] => 05418478
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-23
[patent_title] => 'CMOS differential twisted-pair driver'
[patent_app_type] => 1
[patent_app_number] => 8/100662
[patent_app_country] => US
[patent_app_date] => 1993-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 2507
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 224
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/418/05418478.pdf
[firstpage_image] =>[orig_patent_app_number] => 100662
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/100662 | CMOS differential twisted-pair driver | Jul 29, 1993 | Issued |
Array
(
[id] => 3130193
[patent_doc_number] => 05436577
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-07-25
[patent_title] => 'CMOS tri-state buffer circuit and operation method thereof'
[patent_app_type] => 1
[patent_app_number] => 8/097256
[patent_app_country] => US
[patent_app_date] => 1993-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 6
[patent_no_of_words] => 2090
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/436/05436577.pdf
[firstpage_image] =>[orig_patent_app_number] => 097256
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/097256 | CMOS tri-state buffer circuit and operation method thereof | Jul 22, 1993 | Issued |
Array
(
[id] => 3077623
[patent_doc_number] => 05365124
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-15
[patent_title] => 'BiCMOS logic circuit'
[patent_app_type] => 1
[patent_app_number] => 8/095764
[patent_app_country] => US
[patent_app_date] => 1993-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3309
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/365/05365124.pdf
[firstpage_image] =>[orig_patent_app_number] => 095764
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/095764 | BiCMOS logic circuit | Jul 22, 1993 | Issued |
Array
(
[id] => 3116242
[patent_doc_number] => 05414312
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-05-09
[patent_title] => 'Advanced signal driving buffer with directional input transition detection'
[patent_app_type] => 1
[patent_app_number] => 8/092350
[patent_app_country] => US
[patent_app_date] => 1993-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 2526
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/414/05414312.pdf
[firstpage_image] =>[orig_patent_app_number] => 092350
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/092350 | Advanced signal driving buffer with directional input transition detection | Jul 14, 1993 | Issued |
Array
(
[id] => 3012808
[patent_doc_number] => 05355029
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-11
[patent_title] => 'Staged CMOS output buffer'
[patent_app_type] => 1
[patent_app_number] => 8/090359
[patent_app_country] => US
[patent_app_date] => 1993-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 2967
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/355/05355029.pdf
[firstpage_image] =>[orig_patent_app_number] => 090359
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/090359 | Staged CMOS output buffer | Jul 11, 1993 | Issued |
Array
(
[id] => 3423570
[patent_doc_number] => 05434516
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-07-18
[patent_title] => 'Automatic SCSI termination circuit'
[patent_app_type] => 1
[patent_app_number] => 8/089967
[patent_app_country] => US
[patent_app_date] => 1993-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2079
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/434/05434516.pdf
[firstpage_image] =>[orig_patent_app_number] => 089967
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/089967 | Automatic SCSI termination circuit | Jul 8, 1993 | Issued |
Array
(
[id] => 3433205
[patent_doc_number] => 05455522
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-03
[patent_title] => 'Programmable logic output driver'
[patent_app_type] => 1
[patent_app_number] => 8/082264
[patent_app_country] => US
[patent_app_date] => 1993-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 10
[patent_no_of_words] => 5000
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/455/05455522.pdf
[firstpage_image] =>[orig_patent_app_number] => 082264
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/082264 | Programmable logic output driver | Jun 23, 1993 | Issued |
Array
(
[id] => 3447130
[patent_doc_number] => 05430388
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-07-04
[patent_title] => 'Output noise reduction circuit'
[patent_app_type] => 1
[patent_app_number] => 8/075869
[patent_app_country] => US
[patent_app_date] => 1993-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 5009
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 32
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/430/05430388.pdf
[firstpage_image] =>[orig_patent_app_number] => 075869
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/075869 | Output noise reduction circuit | Jun 10, 1993 | Issued |
Array
(
[id] => 3447520
[patent_doc_number] => 05397937
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-03-14
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/070249
[patent_app_country] => US
[patent_app_date] => 1993-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 31
[patent_figures_cnt] => 31
[patent_no_of_words] => 26366
[patent_no_of_claims] => 57
[patent_no_of_ind_claims] => 12
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/397/05397937.pdf
[firstpage_image] =>[orig_patent_app_number] => 070249
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/070249 | Semiconductor integrated circuit | Jun 1, 1993 | Issued |
Array
(
[id] => 3070430
[patent_doc_number] => 05352940
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-10-04
[patent_title] => 'Ram convertible look-up table based macrocell for PLDs'
[patent_app_type] => 1
[patent_app_number] => 8/068368
[patent_app_country] => US
[patent_app_date] => 1993-05-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2144
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/352/05352940.pdf
[firstpage_image] =>[orig_patent_app_number] => 068368
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/068368 | Ram convertible look-up table based macrocell for PLDs | May 26, 1993 | Issued |
Array
(
[id] => 3495618
[patent_doc_number] => 05440247
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-08-08
[patent_title] => 'Fast CMOS logic with programmable logic control'
[patent_app_type] => 1
[patent_app_number] => 8/066555
[patent_app_country] => US
[patent_app_date] => 1993-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2528
[patent_no_of_claims] => 1
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 289
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/440/05440247.pdf
[firstpage_image] =>[orig_patent_app_number] => 066555
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/066555 | Fast CMOS logic with programmable logic control | May 25, 1993 | Issued |
Array
(
[id] => 3434272
[patent_doc_number] => 05463327
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-10-31
[patent_title] => 'Programmable multiplexer logic cell'
[patent_app_type] => 1
[patent_app_number] => 8/063557
[patent_app_country] => US
[patent_app_date] => 1993-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1656
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/463/05463327.pdf
[firstpage_image] =>[orig_patent_app_number] => 063557
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/063557 | Programmable multiplexer logic cell | May 18, 1993 | Issued |