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Andrew Sanders

Examiner (ID: 3675)

Most Active Art Unit
2509
Art Unit(s)
2504, 2509
Total Applications
463
Issued Applications
431
Pending Applications
2
Abandoned Applications
30

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3050297 [patent_doc_number] => 05334887 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-02 [patent_title] => 'ECL latch circuit' [patent_app_type] => 1 [patent_app_number] => 8/060851 [patent_app_country] => US [patent_app_date] => 1993-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3087 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/334/05334887.pdf [firstpage_image] =>[orig_patent_app_number] => 060851 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/060851
ECL latch circuit May 11, 1993 Issued
Array ( [id] => 2998987 [patent_doc_number] => 05367209 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-22 [patent_title] => 'Field programmable gate array for synchronous and asynchronous operation' [patent_app_type] => 1 [patent_app_number] => 8/056434 [patent_app_country] => US [patent_app_date] => 1993-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9323 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/367/05367209.pdf [firstpage_image] =>[orig_patent_app_number] => 056434 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/056434
Field programmable gate array for synchronous and asynchronous operation Apr 29, 1993 Issued
Array ( [id] => 3038496 [patent_doc_number] => 05329177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-12 [patent_title] => 'Output circuit including current mirror circuits' [patent_app_type] => 1 [patent_app_number] => 8/051566 [patent_app_country] => US [patent_app_date] => 1993-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5019 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/329/05329177.pdf [firstpage_image] =>[orig_patent_app_number] => 051566 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/051566
Output circuit including current mirror circuits Apr 25, 1993 Issued
Array ( [id] => 3050314 [patent_doc_number] => 05334888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-02 [patent_title] => 'Fast exclusive-or and exclusive-nor gates' [patent_app_type] => 1 [patent_app_number] => 8/049558 [patent_app_country] => US [patent_app_date] => 1993-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2817 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/334/05334888.pdf [firstpage_image] =>[orig_patent_app_number] => 049558 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/049558
Fast exclusive-or and exclusive-nor gates Apr 18, 1993 Issued
Array ( [id] => 3447288 [patent_doc_number] => 05430399 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Reset logic circuit and method' [patent_app_type] => 1 [patent_app_number] => 8/049063 [patent_app_country] => US [patent_app_date] => 1993-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3886 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/430/05430399.pdf [firstpage_image] =>[orig_patent_app_number] => 049063 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/049063
Reset logic circuit and method Apr 18, 1993 Issued
Array ( [id] => 3020160 [patent_doc_number] => 05341044 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-08-23 [patent_title] => 'Flexible configuration logic array block for programmable logic devices' [patent_app_type] => 1 [patent_app_number] => 8/049064 [patent_app_country] => US [patent_app_date] => 1993-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3617 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/341/05341044.pdf [firstpage_image] =>[orig_patent_app_number] => 049064 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/049064
Flexible configuration logic array block for programmable logic devices Apr 18, 1993 Issued
Array ( [id] => 2995520 [patent_doc_number] => 05347179 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-09-13 [patent_title] => 'Inverting output driver circuit for reducing electron injection into the substrate' [patent_app_type] => 1 [patent_app_number] => 8/048158 [patent_app_country] => US [patent_app_date] => 1993-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2118 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/347/05347179.pdf [firstpage_image] =>[orig_patent_app_number] => 048158 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/048158
Inverting output driver circuit for reducing electron injection into the substrate Apr 14, 1993 Issued
Array ( [id] => 3043787 [patent_doc_number] => 05376842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-12-27 [patent_title] => 'Integrated circuit with reduced clock skew and divided power supply lines' [patent_app_type] => 1 [patent_app_number] => 8/040244 [patent_app_country] => US [patent_app_date] => 1993-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12159 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/376/05376842.pdf [firstpage_image] =>[orig_patent_app_number] => 040244 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/040244
Integrated circuit with reduced clock skew and divided power supply lines Mar 29, 1993 Issued
Array ( [id] => 3414109 [patent_doc_number] => 05438277 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-01 [patent_title] => 'Ground bounce isolated output buffer' [patent_app_type] => 1 [patent_app_number] => 8/034549 [patent_app_country] => US [patent_app_date] => 1993-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6033 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/438/05438277.pdf [firstpage_image] =>[orig_patent_app_number] => 034549 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/034549
Ground bounce isolated output buffer Mar 18, 1993 Issued
07/997472 HIGH SPEED, LOW POWER INPUT/OUTPUT CIRCUIT FOR A MULTI-CHIP MODULE Mar 17, 1993 Abandoned
Array ( [id] => 3104537 [patent_doc_number] => 05315177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-24 [patent_title] => 'One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture' [patent_app_type] => 1 [patent_app_number] => 8/030896 [patent_app_country] => US [patent_app_date] => 1993-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2966 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/315/05315177.pdf [firstpage_image] =>[orig_patent_app_number] => 030896 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/030896
One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture Mar 11, 1993 Issued
Array ( [id] => 3017962 [patent_doc_number] => 05309044 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-03 [patent_title] => 'Modified widlar source and logic circuit using same' [patent_app_type] => 1 [patent_app_number] => 8/028067 [patent_app_country] => US [patent_app_date] => 1993-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7405 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/309/05309044.pdf [firstpage_image] =>[orig_patent_app_number] => 028067 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/028067
Modified widlar source and logic circuit using same Mar 7, 1993 Issued
Array ( [id] => 3118546 [patent_doc_number] => 05396126 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'FPGA with distributed switch matrix' [patent_app_type] => 1 [patent_app_number] => 8/019963 [patent_app_country] => US [patent_app_date] => 1993-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 3485 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/396/05396126.pdf [firstpage_image] =>[orig_patent_app_number] => 019963 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/019963
FPGA with distributed switch matrix Feb 18, 1993 Issued
Array ( [id] => 3055185 [patent_doc_number] => 05324996 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-28 [patent_title] => 'Floating fault tolerant input buffer circuit' [patent_app_type] => 1 [patent_app_number] => 8/017825 [patent_app_country] => US [patent_app_date] => 1993-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 7312 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/324/05324996.pdf [firstpage_image] =>[orig_patent_app_number] => 017825 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/017825
Floating fault tolerant input buffer circuit Feb 15, 1993 Issued
Array ( [id] => 3041217 [patent_doc_number] => 05300835 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-04-05 [patent_title] => 'CMOS low power mixed voltage bidirectional I/O buffer' [patent_app_type] => 1 [patent_app_number] => 8/016574 [patent_app_country] => US [patent_app_date] => 1993-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7835 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/300/05300835.pdf [firstpage_image] =>[orig_patent_app_number] => 016574 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/016574
CMOS low power mixed voltage bidirectional I/O buffer Feb 9, 1993 Issued
Array ( [id] => 3055225 [patent_doc_number] => 05324998 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-06-28 [patent_title] => 'Zero power reprogrammable flash cell for a programmable logic device' [patent_app_type] => 1 [patent_app_number] => 8/015761 [patent_app_country] => US [patent_app_date] => 1993-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2447 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/324/05324998.pdf [firstpage_image] =>[orig_patent_app_number] => 015761 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/015761
Zero power reprogrammable flash cell for a programmable logic device Feb 9, 1993 Issued
Array ( [id] => 3418262 [patent_doc_number] => 05444406 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-08-22 [patent_title] => 'Self-adjusting variable drive strength buffer circuit and method for controlling the drive strength of a buffer circuit' [patent_app_type] => 1 [patent_app_number] => 8/014955 [patent_app_country] => US [patent_app_date] => 1993-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 14 [patent_no_of_words] => 9503 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/444/05444406.pdf [firstpage_image] =>[orig_patent_app_number] => 014955 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/014955
Self-adjusting variable drive strength buffer circuit and method for controlling the drive strength of a buffer circuit Feb 7, 1993 Issued
Array ( [id] => 3080330 [patent_doc_number] => 05296756 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-03-22 [patent_title] => 'Self adjusting CMOS transmission line driver' [patent_app_type] => 1 [patent_app_number] => 8/014656 [patent_app_country] => US [patent_app_date] => 1993-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2846 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/296/05296756.pdf [firstpage_image] =>[orig_patent_app_number] => 014656 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/014656
Self adjusting CMOS transmission line driver Feb 7, 1993 Issued
Array ( [id] => 3543465 [patent_doc_number] => 05557488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-17 [patent_title] => 'Gimbaled micro-head/flexure/conductor assembly and system' [patent_app_type] => 1 [patent_app_number] => 8/011890 [patent_app_country] => US [patent_app_date] => 1993-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 29 [patent_no_of_words] => 7963 [patent_no_of_claims] => 125 [patent_no_of_ind_claims] => 18 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/557/05557488.pdf [firstpage_image] =>[orig_patent_app_number] => 011890 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/011890
Gimbaled micro-head/flexure/conductor assembly and system Jan 31, 1993 Issued
Array ( [id] => 3448014 [patent_doc_number] => 05467027 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-14 [patent_title] => 'Programmable cell with a programmable component outside the signal path' [patent_app_type] => 1 [patent_app_number] => 8/191557 [patent_app_country] => US [patent_app_date] => 1993-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 2623 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/467/05467027.pdf [firstpage_image] =>[orig_patent_app_number] => 191557 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/191557
Programmable cell with a programmable component outside the signal path Jan 24, 1993 Issued
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