Search

Andrew W. Chriss

Supervisory Patent Examiner (ID: 4510, Phone: (571)272-1774 , Office: P/2479 )

Most Active Art Unit
2472
Art Unit(s)
2472, 2400, 2416, 2609, 2479, 2619, 2419
Total Applications
298
Issued Applications
155
Pending Applications
86
Abandoned Applications
79

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19820696 [patent_doc_number] => 20250078903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => DISCHARGING AN ACCESS DEVICE IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/790372 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790372 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/790372
DISCHARGING AN ACCESS DEVICE IN A MEMORY DEVICE Jul 30, 2024 Pending
Array ( [id] => 20010858 [patent_doc_number] => 20250149080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => MEMORY DEVICE FOR CONTROLLING SHIELDING BIT LINES [patent_app_type] => utility [patent_app_number] => 18/784796 [patent_app_country] => US [patent_app_date] => 2024-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7481 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18784796 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/784796
MEMORY DEVICE FOR CONTROLLING SHIELDING BIT LINES Jul 24, 2024 Pending
Array ( [id] => 19574847 [patent_doc_number] => 20240379139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/783345 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22302 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18783345 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/783345
SEMICONDUCTOR MEMORY DEVICE Jul 23, 2024 Pending
Array ( [id] => 19574847 [patent_doc_number] => 20240379139 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/783345 [patent_app_country] => US [patent_app_date] => 2024-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22302 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18783345 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/783345
SEMICONDUCTOR MEMORY DEVICE Jul 23, 2024 Pending
Array ( [id] => 19548648 [patent_doc_number] => 20240365684 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => SPIN CURRENT MAGNETIZATION ROTATIONAL ELEMENT, SPIN CURRENT MAGNETIZATION ROTATIONAL TYPE MAGNETORESISTIVE ELEMENT, MAGNETIC MEMORY, AND MAGNETIZATION ROTATION METHOD [patent_app_type] => utility [patent_app_number] => 18/771471 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11446 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771471 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771471
SPIN CURRENT MAGNETIZATION ROTATIONAL ELEMENT, SPIN CURRENT MAGNETIZATION ROTATIONAL TYPE MAGNETORESISTIVE ELEMENT, MAGNETIC MEMORY, AND MAGNETIZATION ROTATION METHOD Jul 11, 2024 Pending
Array ( [id] => 20422857 [patent_doc_number] => 20250384942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-18 [patent_title] => ELECTRICAL PARAMETER ADJUSTMENT METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT [patent_app_type] => utility [patent_app_number] => 18/770583 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770583 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770583
ELECTRICAL PARAMETER ADJUSTMENT METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT Jul 10, 2024 Pending
Array ( [id] => 20422857 [patent_doc_number] => 20250384942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-18 [patent_title] => ELECTRICAL PARAMETER ADJUSTMENT METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT [patent_app_type] => utility [patent_app_number] => 18/770583 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770583 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770583
ELECTRICAL PARAMETER ADJUSTMENT METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT Jul 10, 2024 Pending
Array ( [id] => 20422857 [patent_doc_number] => 20250384942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-18 [patent_title] => ELECTRICAL PARAMETER ADJUSTMENT METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT [patent_app_type] => utility [patent_app_number] => 18/770583 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770583 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770583
ELECTRICAL PARAMETER ADJUSTMENT METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT Jul 10, 2024 Pending
Array ( [id] => 19546133 [patent_doc_number] => 20240363169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => MEMORY DEVICE AND ERASING AND VERIFICATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/765164 [patent_app_country] => US [patent_app_date] => 2024-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4045 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18765164 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/765164
MEMORY DEVICE AND ERASING AND VERIFICATION METHOD THEREOF Jul 4, 2024 Pending
Array ( [id] => 19546118 [patent_doc_number] => 20240363154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => MEMORY DEVICE WITH TUNABLE PROBABILISTIC STATE [patent_app_type] => utility [patent_app_number] => 18/763040 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763040 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763040
MEMORY DEVICE WITH TUNABLE PROBABILISTIC STATE Jul 2, 2024 Pending
Array ( [id] => 19546118 [patent_doc_number] => 20240363154 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => MEMORY DEVICE WITH TUNABLE PROBABILISTIC STATE [patent_app_type] => utility [patent_app_number] => 18/763040 [patent_app_country] => US [patent_app_date] => 2024-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18763040 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/763040
MEMORY DEVICE WITH TUNABLE PROBABILISTIC STATE Jul 2, 2024 Pending
Array ( [id] => 20019302 [patent_doc_number] => 20250157524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/754855 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754855 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/754855
SEMICONDUCTOR MEMORY DEVICE Jun 25, 2024 Pending
Array ( [id] => 19483715 [patent_doc_number] => 20240331757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => INTRA-PACKAGE MEMORY DIE COMMUNICATION STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/740242 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740242 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/740242
INTRA-PACKAGE MEMORY DIE COMMUNICATION STRUCTURES Jun 10, 2024 Pending
Array ( [id] => 19483715 [patent_doc_number] => 20240331757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => INTRA-PACKAGE MEMORY DIE COMMUNICATION STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/740242 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740242 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/740242
INTRA-PACKAGE MEMORY DIE COMMUNICATION STRUCTURES Jun 10, 2024 Pending
Array ( [id] => 19483715 [patent_doc_number] => 20240331757 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-03 [patent_title] => INTRA-PACKAGE MEMORY DIE COMMUNICATION STRUCTURES [patent_app_type] => utility [patent_app_number] => 18/740242 [patent_app_country] => US [patent_app_date] => 2024-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15187 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18740242 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/740242
INTRA-PACKAGE MEMORY DIE COMMUNICATION STRUCTURES Jun 10, 2024 Pending
Array ( [id] => 20063097 [patent_doc_number] => 20250201319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => OPERATING METHOD OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/733182 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8468 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18733182 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/733182
OPERATING METHOD OF MEMORY DEVICE Jun 3, 2024 Pending
Array ( [id] => 19603297 [patent_doc_number] => 20240394177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => MEMORY MODULE WITH DISTRIBUTED DATA BUFFERS [patent_app_type] => utility [patent_app_number] => 18/675127 [patent_app_country] => US [patent_app_date] => 2024-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11285 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 666 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675127 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/675127
MEMORY MODULE WITH DISTRIBUTED DATA BUFFERS May 26, 2024 Pending
Array ( [id] => 19603297 [patent_doc_number] => 20240394177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => MEMORY MODULE WITH DISTRIBUTED DATA BUFFERS [patent_app_type] => utility [patent_app_number] => 18/675127 [patent_app_country] => US [patent_app_date] => 2024-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11285 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 666 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18675127 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/675127
MEMORY MODULE WITH DISTRIBUTED DATA BUFFERS May 26, 2024 Pending
Array ( [id] => 19467675 [patent_doc_number] => 20240321345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SRAM STRUCTURE WITH ASYMMETRIC INTERCONNECTION [patent_app_type] => utility [patent_app_number] => 18/672090 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9771 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672090 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672090
SRAM STRUCTURE WITH ASYMMETRIC INTERCONNECTION May 22, 2024 Pending
Array ( [id] => 19452369 [patent_doc_number] => 20240312499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => DIE LOCATION DETECTION FOR GROUPED MEMORY DIES [patent_app_type] => utility [patent_app_number] => 18/672339 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672339 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672339
DIE LOCATION DETECTION FOR GROUPED MEMORY DIES May 22, 2024 Pending
Menu