
Andrew W. Chriss
Supervisory Patent Examiner (ID: 3398, Phone: (571)272-1774 , Office: P/2479 )
| Most Active Art Unit | 2472 |
| Art Unit(s) | 2419, 2472, 2609, 2479, 2619, 2400, 2416 |
| Total Applications | 328 |
| Issued Applications | 163 |
| Pending Applications | 87 |
| Abandoned Applications | 81 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19340326
[patent_doc_number] => 12050514
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-07-30
[patent_title] => Deep neural network implementation for soft decoding of BCH code
[patent_app_type] => utility
[patent_app_number] => 18/184872
[patent_app_country] => US
[patent_app_date] => 2023-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 24738
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18184872
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/184872 | Deep neural network implementation for soft decoding of BCH code | Mar 15, 2023 | Issued |
Array
(
[id] => 18486238
[patent_doc_number] => 20230213581
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-06
[patent_title] => Techniques For Capturing Signals From Logic Circuits At A Logic Analyzer
[patent_app_type] => utility
[patent_app_number] => 18/122238
[patent_app_country] => US
[patent_app_date] => 2023-03-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8961
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18122238
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/122238 | Techniques For Capturing Signals From Logic Circuits At A Logic Analyzer | Mar 15, 2023 | Pending |
Array
(
[id] => 18486952
[patent_doc_number] => 20230214298
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-06
[patent_title] => DATA RECOVERY BASED ON PARITY DATA IN A MEMORY SUB-SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/184395
[patent_app_country] => US
[patent_app_date] => 2023-03-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7732
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18184395
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/184395 | Data recovery based on parity data in a memory sub-system | Mar 14, 2023 | Issued |
Array
(
[id] => 19856949
[patent_doc_number] => 12259783
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-03-25
[patent_title] => Semiconductor device and operation method thereof
[patent_app_type] => utility
[patent_app_number] => 18/183679
[patent_app_country] => US
[patent_app_date] => 2023-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 6
[patent_no_of_words] => 6434
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 75
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18183679
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/183679 | Semiconductor device and operation method thereof | Mar 13, 2023 | Issued |
Array
(
[id] => 18486949
[patent_doc_number] => 20230214295
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-07-06
[patent_title] => ERROR RATES FOR MEMORY WITH BUILT IN ERROR CORRECTION AND DETECTION
[patent_app_type] => utility
[patent_app_number] => 18/121062
[patent_app_country] => US
[patent_app_date] => 2023-03-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10994
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 53
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18121062
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/121062 | Error rates for memory with built in error correction and detection | Mar 13, 2023 | Issued |
Array
(
[id] => 19259457
[patent_doc_number] => 12019511
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-25
[patent_title] => Information processing apparatus, method, and storage medium
[patent_app_type] => utility
[patent_app_number] => 18/181212
[patent_app_country] => US
[patent_app_date] => 2023-03-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 14
[patent_no_of_words] => 9200
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18181212
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/181212 | Information processing apparatus, method, and storage medium | Mar 8, 2023 | Issued |
Array
(
[id] => 18471343
[patent_doc_number] => 20230205629
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-29
[patent_title] => MEMORY SUB-SYSTEM USING PARTIAL SUPERBLOCKS
[patent_app_type] => utility
[patent_app_number] => 18/117555
[patent_app_country] => US
[patent_app_date] => 2023-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7556
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18117555
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/117555 | Memory sub-system using partial superblocks | Mar 5, 2023 | Issued |
Array
(
[id] => 19312997
[patent_doc_number] => 12038809
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-07-16
[patent_title] => Failure analysis for uncorrectable error events
[patent_app_type] => utility
[patent_app_number] => 18/179235
[patent_app_country] => US
[patent_app_date] => 2023-03-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 12
[patent_no_of_words] => 9193
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18179235
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/179235 | Failure analysis for uncorrectable error events | Mar 5, 2023 | Issued |
Array
(
[id] => 18940971
[patent_doc_number] => 20240036110
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-01
[patent_title] => INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND STORAGE MEDIUM
[patent_app_type] => utility
[patent_app_number] => 18/174230
[patent_app_country] => US
[patent_app_date] => 2023-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5924
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18174230
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/174230 | Information processing apparatus, information processing method, and storage medium | Feb 23, 2023 | Issued |
Array
(
[id] => 19426197
[patent_doc_number] => 12085605
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-09-10
[patent_title] => Systems and methods for adjusting input-output impedance for I/O interfaces
[patent_app_type] => utility
[patent_app_number] => 18/173510
[patent_app_country] => US
[patent_app_date] => 2023-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7193
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 186
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18173510
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/173510 | Systems and methods for adjusting input-output impedance for I/O interfaces | Feb 22, 2023 | Issued |
Array
(
[id] => 19568430
[patent_doc_number] => 12143213
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-11-12
[patent_title] => Transmission device, transmission method, reception device, reception method, integrated circuit, and program
[patent_app_type] => utility
[patent_app_number] => 18/112654
[patent_app_country] => US
[patent_app_date] => 2023-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 78
[patent_figures_cnt] => 78
[patent_no_of_words] => 39552
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18112654
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/112654 | Transmission device, transmission method, reception device, reception method, integrated circuit, and program | Feb 21, 2023 | Issued |
Array
(
[id] => 18883760
[patent_doc_number] => 20240007129
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-04
[patent_title] => CONSTRUCTING METHOD, PROCESSING DEVICE, STORAGE MEDIUM AND CODING METHOD
[patent_app_type] => utility
[patent_app_number] => 18/168888
[patent_app_country] => US
[patent_app_date] => 2023-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16878
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18168888
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/168888 | Constructing method, processing device, storage medium and coding method | Feb 13, 2023 | Issued |
Array
(
[id] => 18438370
[patent_doc_number] => 20230185665
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-15
[patent_title] => APPARATUSES, SYSTEMS, AND METHODS FOR FORCED ERROR CHECK AND SCRUB READOUTS
[patent_app_type] => utility
[patent_app_number] => 18/167768
[patent_app_country] => US
[patent_app_date] => 2023-02-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8899
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 45
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18167768
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/167768 | Apparatuses, systems, and methods for forced error check and scrub readouts | Feb 9, 2023 | Issued |
Array
(
[id] => 19152205
[patent_doc_number] => 11977113
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-05-07
[patent_title] => Quantum error-correction in microwave integrated quantum circuits
[patent_app_type] => utility
[patent_app_number] => 18/165272
[patent_app_country] => US
[patent_app_date] => 2023-02-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 15
[patent_no_of_words] => 13749
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18165272
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/165272 | Quantum error-correction in microwave integrated quantum circuits | Feb 5, 2023 | Issued |
Array
(
[id] => 19055692
[patent_doc_number] => 20240097661
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => BI-DIRECTIONAL SCAN FLIP-FLOP CIRCUIT AND METHOD
[patent_app_type] => utility
[patent_app_number] => 18/152017
[patent_app_country] => US
[patent_app_date] => 2023-01-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10096
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 78
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18152017
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/152017 | Bi-directional scan flip-flop circuit and method | Jan 8, 2023 | Issued |
Array
(
[id] => 19198278
[patent_doc_number] => 11995517
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2024-05-28
[patent_title] => Quantum algorithms of logical qubits in a quantum system with physical quibits allowing error correction and increased interqubit-connectivity
[patent_app_type] => utility
[patent_app_number] => 18/094065
[patent_app_country] => US
[patent_app_date] => 2023-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 10090
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18094065
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/094065 | Quantum algorithms of logical qubits in a quantum system with physical quibits allowing error correction and increased interqubit-connectivity | Jan 5, 2023 | Issued |
Array
(
[id] => 18782781
[patent_doc_number] => 11824559
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-11-21
[patent_title] => Techniques for employing polar code in connection with NR (new radio)
[patent_app_type] => utility
[patent_app_number] => 18/094068
[patent_app_country] => US
[patent_app_date] => 2023-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 15264
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18094068
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/094068 | Techniques for employing polar code in connection with NR (new radio) | Jan 5, 2023 | Issued |
Array
(
[id] => 18539472
[patent_doc_number] => 20230244580
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-03
[patent_title] => METHOD, DETECTION CIRCUIT AND ELECTRONIC DEVICE FOR DETECTING TIMING SEQUENCE OF SERIALIZER
[patent_app_type] => utility
[patent_app_number] => 18/089803
[patent_app_country] => US
[patent_app_date] => 2022-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10093
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18089803
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/089803 | Method, detection circuit and electronic device for detecting timing sequence of serializer | Dec 27, 2022 | Issued |
Array
(
[id] => 19734404
[patent_doc_number] => 12212413
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-28
[patent_title] => Techniques for generating and using longer low-density parity check codewords
[patent_app_type] => utility
[patent_app_number] => 18/145844
[patent_app_country] => US
[patent_app_date] => 2022-12-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 30576
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18145844
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/145844 | Techniques for generating and using longer low-density parity check codewords | Dec 21, 2022 | Issued |
Array
(
[id] => 19426610
[patent_doc_number] => 12086028
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-10
[patent_title] => Reduction of errors in data retrieved from a memory device to apply an error correction code of a predetermined code rate
[patent_app_type] => utility
[patent_app_number] => 18/064203
[patent_app_country] => US
[patent_app_date] => 2022-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 8880
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18064203
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/064203 | Reduction of errors in data retrieved from a memory device to apply an error correction code of a predetermined code rate | Dec 8, 2022 | Issued |