Search

Andrew W. Chriss

Supervisory Patent Examiner (ID: 3398, Phone: (571)272-1774 , Office: P/2479 )

Most Active Art Unit
2472
Art Unit(s)
2419, 2472, 2609, 2479, 2619, 2400, 2416
Total Applications
328
Issued Applications
163
Pending Applications
87
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18704492 [patent_doc_number] => 11791008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-17 [patent_title] => Methods and devices for testing multiple memory configurations [patent_app_type] => utility [patent_app_number] => 17/582114 [patent_app_country] => US [patent_app_date] => 2022-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6712 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17582114 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/582114
Methods and devices for testing multiple memory configurations Jan 23, 2022 Issued
Array ( [id] => 18668485 [patent_doc_number] => 11775385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-03 [patent_title] => Targeted command/address parity low lift [patent_app_type] => utility [patent_app_number] => 17/580284 [patent_app_country] => US [patent_app_date] => 2022-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12566 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580284 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/580284
Targeted command/address parity low lift Jan 19, 2022 Issued
Array ( [id] => 19887453 [patent_doc_number] => 12273189 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Indicating a resource set for uplink repetition [patent_app_type] => utility [patent_app_number] => 18/261810 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 17251 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18261810 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/261810
Indicating a resource set for uplink repetition Jan 12, 2022 Issued
Array ( [id] => 18386159 [patent_doc_number] => 11656940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Techniques for managing temporarily retired blocks of a memory system [patent_app_type] => utility [patent_app_number] => 17/574059 [patent_app_country] => US [patent_app_date] => 2022-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 12621 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17574059 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/574059
Techniques for managing temporarily retired blocks of a memory system Jan 11, 2022 Issued
Array ( [id] => 18486944 [patent_doc_number] => 20230214290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-06 [patent_title] => PREVENTING DUPLICATION OF FILES IN A STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/569760 [patent_app_country] => US [patent_app_date] => 2022-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3677 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17569760 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/569760
Preventing duplication of files in a storage device Jan 5, 2022 Issued
Array ( [id] => 18471341 [patent_doc_number] => 20230205627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => DATA STORAGE DEVICE AND METHOD FOR DATA PROTECTION USING XOR PARITY [patent_app_type] => utility [patent_app_number] => 17/563533 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4720 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563533 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/563533
Data storage device and method for data protection using XOR parity Dec 27, 2021 Issued
Array ( [id] => 18191295 [patent_doc_number] => 11581906 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-14 [patent_title] => Hierarchical error correction code decoding using multistage concatenated codes [patent_app_type] => utility [patent_app_number] => 17/646156 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17646156 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/646156
Hierarchical error correction code decoding using multistage concatenated codes Dec 27, 2021 Issued
Array ( [id] => 18402672 [patent_doc_number] => 11664825 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Techniques for employing polar code in connection with NR (new radio) [patent_app_type] => utility [patent_app_number] => 17/562108 [patent_app_country] => US [patent_app_date] => 2021-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15318 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562108 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/562108
Techniques for employing polar code in connection with NR (new radio) Dec 26, 2021 Issued
Array ( [id] => 18130209 [patent_doc_number] => 11556417 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-17 [patent_title] => Reduction of errors in data retrieved from a memory device to apply an error correction code of a predetermined code rate [patent_app_type] => utility [patent_app_number] => 17/559995 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8845 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17559995 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/559995
Reduction of errors in data retrieved from a memory device to apply an error correction code of a predetermined code rate Dec 21, 2021 Issued
Array ( [id] => 18889440 [patent_doc_number] => 11868210 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Memory device crossed matrix parity [patent_app_type] => utility [patent_app_number] => 17/553007 [patent_app_country] => US [patent_app_date] => 2021-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4998 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17553007 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/553007
Memory device crossed matrix parity Dec 15, 2021 Issued
Array ( [id] => 17522017 [patent_doc_number] => 20220107866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-07 [patent_title] => FAST MEMORY ECC ERROR CORRECTION [patent_app_type] => utility [patent_app_number] => 17/550859 [patent_app_country] => US [patent_app_date] => 2021-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7403 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17550859 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/550859
Fast memory ECC error correction Dec 13, 2021 Issued
Array ( [id] => 18802942 [patent_doc_number] => 11836099 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Memory system with cached memory module operations [patent_app_type] => utility [patent_app_number] => 17/548510 [patent_app_country] => US [patent_app_date] => 2021-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 123 [patent_no_of_words] => 10294 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17548510 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/548510
Memory system with cached memory module operations Dec 10, 2021 Issued
Array ( [id] => 17475119 [patent_doc_number] => 20220082623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => PERFORMING SCAN DATA TRANSFER INSIDE MULTI-DIE PACKAGE WITH SERDES FUNCTIONALITY [patent_app_type] => utility [patent_app_number] => 17/532469 [patent_app_country] => US [patent_app_date] => 2021-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17532469 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/532469
Performing scan data transfer inside multi-die package with SERDES functionality Nov 21, 2021 Issued
Array ( [id] => 17706860 [patent_doc_number] => 20220206866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => OPTIMAL CALIBRATION OF GATES IN A QUANTUM COMPUTING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/531520 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12669 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531520 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/531520
Optimal calibration of gates in a quantum computing system Nov 18, 2021 Issued
Array ( [id] => 18015160 [patent_doc_number] => 11507457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Method, electronic device and computer program product for storage management [patent_app_type] => utility [patent_app_number] => 17/531038 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8064 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17531038 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/531038
Method, electronic device and computer program product for storage management Nov 18, 2021 Issued
Array ( [id] => 18378109 [patent_doc_number] => 20230153196 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => CODEWORD REDUNDANCY [patent_app_type] => utility [patent_app_number] => 17/525443 [patent_app_country] => US [patent_app_date] => 2021-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9664 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17525443 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/525443
Codeword redundancy Nov 11, 2021 Issued
Array ( [id] => 18189381 [patent_doc_number] => 11579966 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-14 [patent_title] => Semiconductor system related to performing a training operation [patent_app_type] => utility [patent_app_number] => 17/523644 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 16043 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523644 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/523644
Semiconductor system related to performing a training operation Nov 9, 2021 Issued
Array ( [id] => 18464190 [patent_doc_number] => 11688483 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Managing block retirement for temporary operational conditions [patent_app_type] => utility [patent_app_number] => 17/521785 [patent_app_country] => US [patent_app_date] => 2021-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17521785 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/521785
Managing block retirement for temporary operational conditions Nov 7, 2021 Issued
Array ( [id] => 19633193 [patent_doc_number] => 20240411642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => ECC POWER CONSUMPTION OPTIMIZATION IN MEMORIES [patent_app_type] => utility [patent_app_number] => 18/699834 [patent_app_country] => US [patent_app_date] => 2021-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9960 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18699834 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/699834
ECC power consumption optimization in memories Oct 17, 2021 Issued
Array ( [id] => 18324952 [patent_doc_number] => 20230123080 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => EXECUTE IN PLACE ARCHITECTURE WITH INTEGRITY CHECK [patent_app_type] => utility [patent_app_number] => 17/502300 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6383 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17502300 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/502300
Execute in place architecture with integrity check Oct 14, 2021 Issued
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