Search

Andrew W. Chriss

Supervisory Patent Examiner (ID: 3398, Phone: (571)272-1774 , Office: P/2479 )

Most Active Art Unit
2472
Art Unit(s)
2419, 2472, 2609, 2479, 2619, 2400, 2416
Total Applications
328
Issued Applications
163
Pending Applications
87
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18400940 [patent_doc_number] => 11663078 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-05-30 [patent_title] => In-service scanning and correction of stored data for achieving functional safety [patent_app_type] => utility [patent_app_number] => 17/451049 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8127 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17451049 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/451049
In-service scanning and correction of stored data for achieving functional safety Oct 14, 2021 Issued
Array ( [id] => 18072755 [patent_doc_number] => 11531589 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-20 [patent_title] => Decoding method, memory storage device, and memory control circuit unit [patent_app_type] => utility [patent_app_number] => 17/495815 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 10128 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495815 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/495815
Decoding method, memory storage device, and memory control circuit unit Oct 6, 2021 Issued
Array ( [id] => 18387887 [patent_doc_number] => 11658685 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-23 [patent_title] => Memory with multi-mode ECC engine [patent_app_type] => utility [patent_app_number] => 17/494361 [patent_app_country] => US [patent_app_date] => 2021-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6934 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17494361 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/494361
Memory with multi-mode ECC engine Oct 4, 2021 Issued
Array ( [id] => 18899468 [patent_doc_number] => 20240014953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => METHOD FOR ESTIMATING BIT ERROR PROBABILITY USING ERROR RATE RATIO OF FRAME SYNCHRONIZATION WORD [patent_app_type] => utility [patent_app_number] => 18/255555 [patent_app_country] => US [patent_app_date] => 2021-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18255555 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/255555
Method for estimating bit error probability using error rate ratio of frame synchronization word Sep 30, 2021 Issued
Array ( [id] => 17345791 [patent_doc_number] => 20220012122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-13 [patent_title] => DYNAMIC CONTROL OF ERROR MANAGEMENT AND SIGNALING [patent_app_type] => utility [patent_app_number] => 17/486751 [patent_app_country] => US [patent_app_date] => 2021-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22023 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17486751 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/486751
Dynamic control of error management and signaling Sep 26, 2021 Issued
Array ( [id] => 18285128 [patent_doc_number] => 20230100600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => MIXED CURRENT-FORCED READ SCHEME FOR RERAM ARRAY WITH SELECTOR [patent_app_type] => utility [patent_app_number] => 17/485129 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25359 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485129 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485129
Mixed current-forced read scheme for MRAM array with selector Sep 23, 2021 Issued
Array ( [id] => 18268201 [patent_doc_number] => 20230089443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-23 [patent_title] => METHOD TO INCREASE THE USABLE WORD WIDTH OF A MEMORY PROVIDING AN ERROR CORRECTION SCHEME [patent_app_type] => utility [patent_app_number] => 17/477871 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8223 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17477871 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/477871
Method to increase the usable word width of a memory providing an error correction scheme Sep 16, 2021 Issued
Array ( [id] => 17907321 [patent_doc_number] => 11461175 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-10-04 [patent_title] => Signature generation by a data processing device [patent_app_type] => utility [patent_app_number] => 17/447954 [patent_app_country] => US [patent_app_date] => 2021-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10668 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447954 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/447954
Signature generation by a data processing device Sep 16, 2021 Issued
Array ( [id] => 18401937 [patent_doc_number] => 11664082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Capacitor health check [patent_app_type] => utility [patent_app_number] => 17/476115 [patent_app_country] => US [patent_app_date] => 2021-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17476115 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/476115
Capacitor health check Sep 14, 2021 Issued
Array ( [id] => 17478414 [patent_doc_number] => 20220085918 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => REPETITION TRANSMISSIONS WITH OVERLAPPING RESOURCES [patent_app_type] => utility [patent_app_number] => 17/471088 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22312 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471088 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/471088
Repetition transmissions with overlapping resources Sep 8, 2021 Issued
Array ( [id] => 18230165 [patent_doc_number] => 20230069159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => MEMORY SUB-SYSTEM USING PARTIAL SUPERBLOCKS [patent_app_type] => utility [patent_app_number] => 17/464290 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7519 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17464290 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/464290
Memory sub-system using partial superblocks Aug 31, 2021 Issued
Array ( [id] => 18330766 [patent_doc_number] => 11636008 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Tracking host-provided metadata in a memory sub-system [patent_app_type] => utility [patent_app_number] => 17/464449 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 10355 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17464449 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/464449
Tracking host-provided metadata in a memory sub-system Aug 31, 2021 Issued
Array ( [id] => 17294170 [patent_doc_number] => 20210390009 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-16 [patent_title] => Automotive Electronic Control Unit Reliability and Safety During Power Standby Mode [patent_app_type] => utility [patent_app_number] => 17/460118 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5789 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17460118 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/460118
Automotive electronic control unit reliability and safety during power standby mode Aug 26, 2021 Issued
Array ( [id] => 18493413 [patent_doc_number] => 11698830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Semiconductor memory [patent_app_type] => utility [patent_app_number] => 17/445984 [patent_app_country] => US [patent_app_date] => 2021-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5786 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445984 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/445984
Semiconductor memory Aug 25, 2021 Issued
Array ( [id] => 17809477 [patent_doc_number] => 20220261312 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-18 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/412026 [patent_app_country] => US [patent_app_date] => 2021-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10612 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17412026 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/412026
Memory system Aug 24, 2021 Issued
Array ( [id] => 18015155 [patent_doc_number] => 11507452 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-22 [patent_title] => Error checking for systolic array computation [patent_app_type] => utility [patent_app_number] => 17/410558 [patent_app_country] => US [patent_app_date] => 2021-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 16729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17410558 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/410558
Error checking for systolic array computation Aug 23, 2021 Issued
Array ( [id] => 17276585 [patent_doc_number] => 20210382783 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => DETECT AND TRIAGE DATA INTEGRITY ISSUE FOR VIRTUAL MACHINE [patent_app_type] => utility [patent_app_number] => 17/405568 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6851 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17405568 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/405568
Detect and triage data integrity issue for virtual machine Aug 17, 2021 Issued
Array ( [id] => 18046703 [patent_doc_number] => 11520657 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-06 [patent_title] => Defect detection in memory based on active monitoring of read operations [patent_app_type] => utility [patent_app_number] => 17/445392 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7452 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445392 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/445392
Defect detection in memory based on active monitoring of read operations Aug 17, 2021 Issued
Array ( [id] => 17507502 [patent_doc_number] => 20220100605 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => PREEMPTIVE READ VERIFICATION AFTER HARDWARE WRITE BACK [patent_app_type] => utility [patent_app_number] => 17/445345 [patent_app_country] => US [patent_app_date] => 2021-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6594 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17445345 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/445345
Preemptive read verification after hardware write back Aug 17, 2021 Issued
Array ( [id] => 17230576 [patent_doc_number] => 20210357133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => ERASE DETECTION LOGIC FOR A STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 17/388982 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8898 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17388982 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/388982
Error correction bypass for erased pages Jul 28, 2021 Issued
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