Search

Andrew W. Chriss

Supervisory Patent Examiner (ID: 3398, Phone: (571)272-1774 , Office: P/2479 )

Most Active Art Unit
2472
Art Unit(s)
2419, 2472, 2609, 2479, 2619, 2400, 2416
Total Applications
328
Issued Applications
163
Pending Applications
87
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17715315 [patent_doc_number] => 11379306 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-07-05 [patent_title] => Method for radiation hardening synchronous DRAM [patent_app_type] => utility [patent_app_number] => 17/388690 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17388690 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/388690
Method for radiation hardening synchronous DRAM Jul 28, 2021 Issued
Array ( [id] => 17204266 [patent_doc_number] => 20210344361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-04 [patent_title] => BUTTERFLY NETWORK ON LOAD DATA RETURN [patent_app_type] => utility [patent_app_number] => 17/378886 [patent_app_country] => US [patent_app_date] => 2021-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17378886 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/378886
Butterfly network on load data return Jul 18, 2021 Issued
Array ( [id] => 18189386 [patent_doc_number] => 11579971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Apparatuses, systems, and methods for forced error check and scrub readouts [patent_app_type] => utility [patent_app_number] => 17/375957 [patent_app_country] => US [patent_app_date] => 2021-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8864 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17375957 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/375957
Apparatuses, systems, and methods for forced error check and scrub readouts Jul 13, 2021 Issued
Array ( [id] => 18414838 [patent_doc_number] => 11669380 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Dynamic programming of page margins [patent_app_type] => utility [patent_app_number] => 17/373667 [patent_app_country] => US [patent_app_date] => 2021-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 17081 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17373667 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/373667
Dynamic programming of page margins Jul 11, 2021 Issued
Array ( [id] => 17187274 [patent_doc_number] => 20210334159 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => METHODS FOR ERROR COUNT REPORTING WITH SCALED ERROR COUNT INFORMATION, AND MEMORY DEVICES EMPLOYING THE SAME [patent_app_type] => utility [patent_app_number] => 17/372453 [patent_app_country] => US [patent_app_date] => 2021-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4030 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372453 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/372453
Methods for error count reporting with scaled error count information, and memory devices employing the same Jul 9, 2021 Issued
Array ( [id] => 18950784 [patent_doc_number] => 11894087 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Test circuit [patent_app_type] => utility [patent_app_number] => 17/440114 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3955 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17440114 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/440114
Test circuit Jul 6, 2021 Issued
Array ( [id] => 18074289 [patent_doc_number] => 11533135 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-20 [patent_title] => Memory conservation in delta-compressed message transmission and recovery [patent_app_type] => utility [patent_app_number] => 17/366680 [patent_app_country] => US [patent_app_date] => 2021-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6597 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17366680 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/366680
Memory conservation in delta-compressed message transmission and recovery Jul 1, 2021 Issued
Array ( [id] => 17706886 [patent_doc_number] => 20220206892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/367189 [patent_app_country] => US [patent_app_date] => 2021-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7085 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17367189 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/367189
Memory system Jul 1, 2021 Issued
Array ( [id] => 17514665 [patent_doc_number] => 11293808 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-05 [patent_title] => Integrated circuit and method for capturing baseline die temperature data [patent_app_type] => utility [patent_app_number] => 17/363739 [patent_app_country] => US [patent_app_date] => 2021-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 8028 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17363739 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/363739
Integrated circuit and method for capturing baseline die temperature data Jun 29, 2021 Issued
Array ( [id] => 18917664 [patent_doc_number] => 11879940 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Dynamic generation of ATPG mode signals for testing multipath memory circuit [patent_app_type] => utility [patent_app_number] => 17/355386 [patent_app_country] => US [patent_app_date] => 2021-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4273 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17355386 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/355386
Dynamic generation of ATPG mode signals for testing multipath memory circuit Jun 22, 2021 Issued
Array ( [id] => 18087332 [patent_doc_number] => 11537467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-12-27 [patent_title] => Memory, memory system, and operation method of memory [patent_app_type] => utility [patent_app_number] => 17/354355 [patent_app_country] => US [patent_app_date] => 2021-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3835 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17354355 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/354355
Memory, memory system, and operation method of memory Jun 21, 2021 Issued
Array ( [id] => 18030706 [patent_doc_number] => 11513895 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-11-29 [patent_title] => Data storage device processing problematic patterns as erasures [patent_app_type] => utility [patent_app_number] => 17/345434 [patent_app_country] => US [patent_app_date] => 2021-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2999 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17345434 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/345434
Data storage device processing problematic patterns as erasures Jun 10, 2021 Issued
Array ( [id] => 17853855 [patent_doc_number] => 20220283897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => VERIFYING METHOD FOR ECC CIRCUIT OF SRAM [patent_app_type] => utility [patent_app_number] => 17/336818 [patent_app_country] => US [patent_app_date] => 2021-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6695 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17336818 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/336818
Verifying method for ECC circuit of SRAM Jun 1, 2021 Issued
Array ( [id] => 18651907 [patent_doc_number] => 20230297743 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => DEEP NEURAL NETWORKS FOR SYNTHESIS AND OPTIMIZATION OF SMOOTH SURFACED 3D OBJECTS [patent_app_type] => utility [patent_app_number] => 17/999941 [patent_app_country] => US [patent_app_date] => 2021-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17999941 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/999941
DEEP NEURAL NETWORKS FOR SYNTHESIS AND OPTIMIZATION OF SMOOTH SURFACED 3D OBJECTS Jun 1, 2021 Abandoned
Array ( [id] => 17651464 [patent_doc_number] => 11354191 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-06-07 [patent_title] => Erasure coding in a large geographically diverse data storage system [patent_app_type] => utility [patent_app_number] => 17/333793 [patent_app_country] => US [patent_app_date] => 2021-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 17621 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17333793 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/333793
Erasure coding in a large geographically diverse data storage system May 27, 2021 Issued
Array ( [id] => 19078451 [patent_doc_number] => 11947819 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Method and system for testing conversion relationship between block reading and page reading in flash memory chip [patent_app_type] => utility [patent_app_number] => 18/040299 [patent_app_country] => US [patent_app_date] => 2021-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4378 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 395 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18040299 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/040299
Method and system for testing conversion relationship between block reading and page reading in flash memory chip May 26, 2021 Issued
Array ( [id] => 17744389 [patent_doc_number] => 11392457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-19 [patent_title] => Error correction method of a memory system [patent_app_type] => utility [patent_app_number] => 17/332448 [patent_app_country] => US [patent_app_date] => 2021-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 16504 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17332448 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/332448
Error correction method of a memory system May 26, 2021 Issued
Array ( [id] => 17083453 [patent_doc_number] => 20210278459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => PATH BASED CONTROLS FOR ATE MODE TESTING OF MULTICELL MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/330653 [patent_app_country] => US [patent_app_date] => 2021-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3989 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17330653 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/330653
Path based controls for ATE mode testing of multicell memory circuit May 25, 2021 Issued
Array ( [id] => 17572902 [patent_doc_number] => 11321171 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-05-03 [patent_title] => Memory operations management in computing systems [patent_app_type] => utility [patent_app_number] => 17/328891 [patent_app_country] => US [patent_app_date] => 2021-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 8170 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17328891 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/328891
Memory operations management in computing systems May 23, 2021 Issued
Array ( [id] => 17582627 [patent_doc_number] => 20220139482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => SEMICONDUCTOR MEMORY DEVICES AND METHODS OF OPERATING SEMICONDUCTOR MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/326416 [patent_app_country] => US [patent_app_date] => 2021-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12850 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17326416 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/326416
Semiconductor memory devices and methods of operating semiconductor memory devices May 20, 2021 Issued
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