Search

Andrew W. Chriss

Supervisory Patent Examiner (ID: 3398, Phone: (571)272-1774 , Office: P/2479 )

Most Active Art Unit
2472
Art Unit(s)
2419, 2472, 2609, 2479, 2619, 2400, 2416
Total Applications
328
Issued Applications
163
Pending Applications
87
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14544189 [patent_doc_number] => 20190207716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-04 [patent_title] => Video encoding apparatus for rearranging packet transmission order and procedure of operating video encoding apparatus [patent_app_type] => utility [patent_app_number] => 15/999182 [patent_app_country] => US [patent_app_date] => 2018-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3852 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15999182 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/999182
Video encoding apparatus for rearranging packet transmission order and procedure of operating video encoding apparatus Aug 16, 2018 Abandoned
Array ( [id] => 14906017 [patent_doc_number] => 20190296774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-09-26 [patent_title] => MEMORY SYSTEM AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 16/104233 [patent_app_country] => US [patent_app_date] => 2018-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14901 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16104233 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/104233
Memory system and control method Aug 16, 2018 Issued
Array ( [id] => 13845391 [patent_doc_number] => 20190026180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => PREDICTIVE CACHING FOR CHECK WORD SNOOPING IN HIGH PERFORMANCE FICON [patent_app_type] => utility [patent_app_number] => 16/047585 [patent_app_country] => US [patent_app_date] => 2018-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16047585 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/047585
Predictive caching for check word snooping in high performance ficon Jul 26, 2018 Issued
Array ( [id] => 16186888 [patent_doc_number] => 10720224 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-21 [patent_title] => Protocol independent testing of memory devices using a loopback [patent_app_type] => utility [patent_app_number] => 16/038517 [patent_app_country] => US [patent_app_date] => 2018-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 8164 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16038517 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/038517
Protocol independent testing of memory devices using a loopback Jul 17, 2018 Issued
Array ( [id] => 17999740 [patent_doc_number] => 11500848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-15 [patent_title] => Method for determining the integrity of navigation data of a control unit of an automotive vehicle [patent_app_type] => utility [patent_app_number] => 16/631941 [patent_app_country] => US [patent_app_date] => 2018-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3384 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 385 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16631941 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/631941
Method for determining the integrity of navigation data of a control unit of an automotive vehicle Jul 16, 2018 Issued
Array ( [id] => 13560297 [patent_doc_number] => 20180331696 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => LOW POWER SCHEME FOR BIT FLIPPING LOW DENSITY PARITY CHECK DECODER [patent_app_type] => utility [patent_app_number] => 16/029677 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16029677 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/029677
LOW POWER SCHEME FOR BIT FLIPPING LOW DENSITY PARITY CHECK DECODER Jul 8, 2018 Abandoned
Array ( [id] => 15077239 [patent_doc_number] => 10468114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-05 [patent_title] => Shared error detection and correction memory [patent_app_type] => utility [patent_app_number] => 16/013290 [patent_app_country] => US [patent_app_date] => 2018-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 9033 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16013290 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/013290
Shared error detection and correction memory Jun 19, 2018 Issued
Array ( [id] => 13998125 [patent_doc_number] => 20190068220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-02-28 [patent_title] => MEMORY SYSTEM WITH LDPC DECODER AND METHOD OF OPERATING SUCH MEMORY SYSTEM AND LDPC DECODER [patent_app_type] => utility [patent_app_number] => 16/010026 [patent_app_country] => US [patent_app_date] => 2018-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5912 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16010026 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/010026
Memory system with LDPC decoder and method of operating such memory system and LDPC decoder Jun 14, 2018 Issued
Array ( [id] => 14442123 [patent_doc_number] => 20190178934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-13 [patent_title] => Pin Connection Testing System For Connector, And Method Thereof [patent_app_type] => utility [patent_app_number] => 16/009888 [patent_app_country] => US [patent_app_date] => 2018-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5804 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16009888 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/009888
Pin connection testing system for connector, and method thereof Jun 14, 2018 Issued
Array ( [id] => 15732945 [patent_doc_number] => 10614905 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-07 [patent_title] => System for testing memory and method thereof [patent_app_type] => utility [patent_app_number] => 16/009548 [patent_app_country] => US [patent_app_date] => 2018-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3908 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16009548 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/009548
System for testing memory and method thereof Jun 14, 2018 Issued
Array ( [id] => 16567584 [patent_doc_number] => 10892966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-12 [patent_title] => Monitoring interconnect failures over time [patent_app_type] => utility [patent_app_number] => 15/995819 [patent_app_country] => US [patent_app_date] => 2018-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5222 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15995819 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/995819
Monitoring interconnect failures over time May 31, 2018 Issued
Array ( [id] => 16069067 [patent_doc_number] => 10693501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Method and apparatus for controlling interleaving depth [patent_app_type] => utility [patent_app_number] => 15/989441 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9895 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15989441 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/989441
Method and apparatus for controlling interleaving depth May 24, 2018 Issued
Array ( [id] => 14613551 [patent_doc_number] => 10359470 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-23 [patent_title] => Semiconductor integrated circuit and test method thereof [patent_app_type] => utility [patent_app_number] => 15/989593 [patent_app_country] => US [patent_app_date] => 2018-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5111 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15989593 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/989593
Semiconductor integrated circuit and test method thereof May 24, 2018 Issued
Array ( [id] => 16747124 [patent_doc_number] => 10972133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-06 [patent_title] => Flag fault-tolerant error correction with arbitrary distance codes [patent_app_type] => utility [patent_app_number] => 15/986658 [patent_app_country] => US [patent_app_date] => 2018-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 49 [patent_no_of_words] => 22622 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15986658 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/986658
Flag fault-tolerant error correction with arbitrary distance codes May 21, 2018 Issued
Array ( [id] => 16069011 [patent_doc_number] => 10693473 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Multi-modal data-driven clock recovery circuit [patent_app_type] => utility [patent_app_number] => 15/986582 [patent_app_country] => US [patent_app_date] => 2018-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 47 [patent_no_of_words] => 17315 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15986582 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/986582
Multi-modal data-driven clock recovery circuit May 21, 2018 Issued
Array ( [id] => 15184421 [patent_doc_number] => 20190362802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-28 [patent_title] => VERIFICATION OF A BRIDGE HAVING A LATE WRITE BUFFER [patent_app_type] => utility [patent_app_number] => 15/986322 [patent_app_country] => US [patent_app_date] => 2018-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8428 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15986322 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/986322
Verification of a bridge having a late write buffer May 21, 2018 Issued
Array ( [id] => 13595347 [patent_doc_number] => 20180349222 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => SEMICONDUCTOR DEVICE AND MEMORY MODULE [patent_app_type] => utility [patent_app_number] => 15/984572 [patent_app_country] => US [patent_app_date] => 2018-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15605 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15984572 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/984572
Semiconductor device and memory module May 20, 2018 Issued
Array ( [id] => 15952877 [patent_doc_number] => 10664346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Parity log with by-pass [patent_app_type] => utility [patent_app_number] => 15/984135 [patent_app_country] => US [patent_app_date] => 2018-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9773 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15984135 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/984135
Parity log with by-pass May 17, 2018 Issued
Array ( [id] => 15954809 [patent_doc_number] => 10665317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Method of ECC encoding a DRAM and a DRAM [patent_app_type] => utility [patent_app_number] => 15/982097 [patent_app_country] => US [patent_app_date] => 2018-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4874 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15982097 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/982097
Method of ECC encoding a DRAM and a DRAM May 16, 2018 Issued
Array ( [id] => 16646264 [patent_doc_number] => 10924136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Transmission device, transmission method, reception device, and reception method [patent_app_type] => utility [patent_app_number] => 16/606935 [patent_app_country] => US [patent_app_date] => 2018-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 116 [patent_figures_cnt] => 131 [patent_no_of_words] => 53487 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 24 [patent_words_short_claim] => 813 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16606935 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/606935
Transmission device, transmission method, reception device, and reception method May 16, 2018 Issued
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